Draft 9/ 9/ 2008
PDF: 09005aef80814e61/Source: 09005aef807f8acb Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD18C64_128x72A.fm - Rev. D 9/08 EN
9 ©2004 Micron Technology, Inc. All rights reserved
512MB, 1GB (x72, ECC, DR) 184-Pin DDR SDRAM UDIMM
Electrical Specifications
Idd Specifications
Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks are
in Idd2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
Table 9: Idd Specifications and Conditions – 512MB (Die Revision K)
Values shown for the MT46V32M8 DDR SDRAM only and are computed from values specified in the
256Mb (32 Meg x 8) component data sheet
Parameter/Condition Symbol -40B -335 Units
Operating one bank active-precharge current:
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN);
DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs
changing once every two clock cycles
Idd0
1
936 846 mA
Operating one bank active-read-precharge current: BL = 2;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); Iout = 0mA; Address and control inputs changing once per clock cycle
Idd1
1
1,116 1,071 mA
Precharge power-down standby current: All device banks idle; Power-down
mode;
t
CK =
t
CK (MIN); CKE = LOW
Idd2P
2
72 72 mA
Idle standby current: CS# = HIGH; All device banks idle;
t
CK =
t
CK (MIN);
CKE = HIGH; Address and other control inputs
changing once per clock cycle; V
in
=V
ref
for DQ, DQS, and DM
Idd2F
2
900 900 mA
Active power-down standby current: One device bank active; Power-down mode;
t
CK =
t
CK (MIN); CKE = LOW
Idd3P
2
630 540 mA
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active;
t
RC =
t
RAS (MAX);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing twice per clock
cycle; Address and other control inputs changing once per clock cycle
Idd3N
2
1,080 990 mA
Operating burst read current: BL = 2; Continuous burst reads; One device bank
active; Address and control inputs changing once per clock cycle;
t
CK =
t
CK (MIN);
Iout = 0mA
Idd4R
1
1,656 1,476 mA
Operating burst write current: BL = 2; Continuous burst writes; One device bank
active; Address and control inputs changing once per clock cycle;
t
CK =
t
CK (MIN); DQ,
DM, and DQS inputs changing twice per clock cycle
Idd4W
1
1,656 1,476 mA
Auto refresh current
t
REFC =
t
RFC (MIN) Idd5
2
2,880 2,880 mA
t
REFC = 15.625µs Idd5A
2
72 72 mA
Self refresh current: CKE ≤ 0.2V Idd6
2
36 36 mA
Operating bank interleave read current: Four device bank interleaving reads
(BL = 4) with auto precharge;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); Address and control
inputs change only during active READ or WRITE commands
Idd7
1
2,646 2,466 mA
