6
ACPL-M72U Low Power Mode Switching Speci cations
Over recommended temperature (-40°C to +125°C), 3.0V ≤ V
DD
≤ 5.5V. All typical speci cations at +25°C and VDD = 5V
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig Note
Propagation Delay Time to
Logic Low Output
[1]
t
PHL
60 100 ns I
F
=4mA, C
L
=15pF 7,8,
9,10,
14
1,2,3
Propagation Delay Time to
Logic High Output
[1]
t
PLH
35 100 ns
Pulse Width Distortion
[2]
PWD 25 50 ns
Propagation Delay Skew
[3]
t
PSK
60 ns
Output Rise Time
(10% – 90%)
t
R
10 ns
Output Fall Time
(90% - 10%)
t
F
10 ns
Common Mode Transient
Immunity at Logic High
Output
[4]
| CM
H
|25 40
kV/s
Using Avago LED Driving
Circuit,
V
IN
=0V, R
1
=350+/-5% ,
R
2
=350+/-5%, V
CM
=1000V,
T
A
=25°C
15 4
Common Mode Transient
Immunity at Logic High
Output
[5]
| CM
L
|25 40
kV/s
Using Avago LED Driving
Circuit,
V
IN
=4.5-5.5V, R
1
=350+/-5% ,
R
2
=350, V
CM
=1000V, T
A
=25°C
16 5
Package Characteristics
All Typical at T
A
= 25°C.
Parameter Symbol Min. Typ. Max. Units Test Conditions
Input-Output Momentary
Withstand Voltage
V
ISO
3750 V
rms
RH ≤ 50%, t = 1 min.,
T
A
= 25°C
Input-Output Resistance R
I-O
10
14
V
I-O
= 500 V dc
Input-Output Capacitance C
I-O
0.6 pF f = 1 MHz, T
A
= 25°C
Notes:
1. t
PHL
propagation delay is measured from the 50% (Vin or If) on the rising edge of the input pulse to 0.8V on the falling edge of the V
O
signal. t
PLH
propagation delay is measured from the 50% (Vin or If) on the falling edge of the input pulse to the 80% level of the rising edge of the V
O
signal.
2. PWD is de ned as |t
PHL
- t
PLH
|.
3. t
PSK
is equal to the magnitude of the worst case di erence in t
PHL
and/or t
PLH
that will be seen between units at any given temperature within the
recommended operating conditions.
4. CM
H
is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.
5. CM
L
is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.
