ADM1030
http://onsemi.com
17
Filtered Control Mode
The Automatic Fan Speed Control Loop reacts
instantaneously to changes in temperature, i.e., the PWM
duty cycle will respond immediately to temperature change.
In certain circumstances, we may not want the PWM output
to react instantaneously to temperature changes. If
significant variations in temperature were found in a system,
it would have the effect of changing the fan speed, which
could be obvious to someone in close proximity. One way to
improve the system’s acoustics would be to slow down the
loop so that the fan ramps slowly to its newly calculated fan
speed. This also ensures that temperature transients will
effectively be ignored, and the fan’s operation will be
smooth.
There are two means by which to apply filtering to the
Automatic Fan Speed Control Loop. The first method is to
ramp the fan speed at a predetermined rate, to its newly
calculated value instead of jumping directly to the new fan
speed. The second approach involves changing the on-chip
ADC sample rate, to change the number of temperature
readings taken per second.
The filtered mode on the ADM1030 is invoked by setting
Bit 0 of the Fan Filter Register (Register 0x23). Once the Fan
Filter Register has been written to, and all other control loop
parameters (T
MIN
, T
RANGE
, etc.) have been programmed,
the device may be placed into Automatic Fan Speed Control
Mode by setting Bit 7 of Configuration Register 1 (Register
0x00) to 1.
Effect of Ramp Rate on Filtered Mode
Bits <6:5> of the Fan Filter Register determine the ramp
rate in Filtered Mode. The PWM_OUT signal driving the
fan will have a period, T, given by the PWM_OUT drive
frequency, f, since T = 1/f. For a given PWM period, T, the
PWM period is subdivided into 240 equal time slots. One
time slot corresponds to the smallest possible increment in
PWM duty cycle. A PWM signal of 33% duty cycle will thus
be high for 1/3 240 time slots and low for 2/3 240 time
slots. Therefore, 33% PWM duty cycle corresponds to a
signal which is high for 80 time slots and low for 160 time
slots.
Figure 27. 33% PWM Duty Cycle Represented
in Time Slots
80 TIME
SLOTS
160 TIME
SLOTS
PWM_OUT
33% DUTY
CYCLE
PWM OUTPUT
(ONE PERIOD) =
240 TIME SLOTS
The ramp rates in Filtered Mode are selectable between
1, 2, 4, and 8. The ramp rates are actually discrete time slots.
For example, if the ramp rate = 8, then eight time slots will
be added to the PWM_OUT high duty cycle each time the
PWM_OUT duty cycle needs to be increased. Figure 28
shows how the Filtered Mode algorithm operates.
Figure 28. Filtered Mode Algorithm
READ
TEMPERATURE
CALCULATE
NEW PWM
DUTY CYCLE
INCREMENT
PREVIOUS PWM
VALUE BY RAMP
RATE
DECREMENT
PREVIOUS
PWM VALUE
BY RAMP RATE
IS NEW
PWM VALUE >
PREVIOUS
VAULE?
NO
YES
The Filtered Mode algorithm calculates a new PWM duty
cycle based on the temperature measured. If the new PWM
duty cycle value is greater than the previous PWM value, the
previous PWM duty cycle value is incremented by either
1, 2, 4, or 8 time slots (depending on the setting of bits <6:5>
of the Fan Filter Register). If the new PWM duty cycle value
is less than the previous PWM value, the previous PWM
duty cycle is decremented by 1, 2, 4, or 8 time slots. Each
time the PWM duty cycle is incremented or decremented, it
is stored as the previous PWM duty cycle for the next
comparison.
So what does an increase of 1, 2, 4, or 8 time slots actually
mean in terms of PWM duty cycle?
A Ramp Rate of 1 corresponds to one time slot, which is
1/240 of the PWM period. In Filtered Auto Fan Speed
Control Mode, incrementing or decrementing by 1 changes
the PWM output duty cycle by 0.416%.
Table 12. EFFECT OF RAMP RATES ON PWM_OUT
Ramp Rate PWM Duty Cycle Change
1 0.416%
2 0.833%
4 1.66%
8 3.33%
So programming a ramp rate of 1, 2, 4, or 8 simply
increases or decreases the PWM duty cycle by the amounts
shown in Table 9, depending on whether the temperature is
increasing or decreasing.
Figure 29 shows remote temperature plotted against
PWM duty cycle for Filtered Mode. The ADC sample rate
