MP1584 – 3A, 1.5MHz, 28V STEP-DOWN CONVERTER
MP1584 Rev. 1.0 www.MonolithicPower.com 12
8/8/2011 MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
The input capacitor (C1) can be electrolytic,
tantalum or ceramic. When using electrolytic or
tantalum capacitors, a small, high quality
ceramic capacitor, i.e. 0.1F, should be placed
as close to the IC as possible. When using
ceramic capacitors, make sure that they have
enough capacitance to provide sufficient charge
to prevent excessive voltage ripple at input. The
input voltage ripple caused by capacitance can
be estimated by:
IN
OUT
IN
OUT
S
LOAD
IN
V
V
1
V
V
1Cf
I
V
Output Capacitor
The output capacitor (C2) is required to
maintain the DC output voltage. Ceramic,
tantalum, or low ESR electrolytic capacitors are
recommended. Low ESR capacitors are
preferred to keep the output voltage ripple low.
The output voltage ripple can be estimated by:
2Cf8
1
R
V
V
1
Lf
V
V
S
ESR
IN
OUT
S
OUT
OUT
Where L is the inductor value and R
ESR is the
equivalent series resistance (ESR) value of the
output capacitor.
In the case of ceramic capacitors, the
impedance at the switching frequency is
dominated by the capacitance. The output
voltage ripple is mainly caused by the
capacitance. For simplification, the output
voltage ripple can be estimated by:
IN
OUT
2
S
OUT
OUT
V
V
1
2CLf8
V
V
In the case of tantalum or electrolytic capacitors,
the ESR dominates the impedance at the
switching frequency. For simplification, the
output ripple can be approximated to:
ESR
IN
OUT
S
OUT
OUT
R
V
V
1
Lf
V
V
The characteristics of the output capacitor also
affect the stability of the regulation system. The
MP1584 can be optimized for a wide range of
capacitance and ESR values.
Compensation Components
MP1584 employs current mode control for easy
compensation and fast transient response. The
system stability and transient response are
controlled through the COMP pin. COMP pin is
the output of the internal error amplifier. A
series capacitor-resistor combination sets a
pole-zero combination to control the
characteristics of the control system. The DC
gain of the voltage feedback loop is given by:
OUT
FB
VEACSLOADVDC
V
V
AGRA
Where A
VEA is the error amplifier voltage gain,
200V/V; G
CS is the current sense
transconductance, 9A/V; R
LOAD is the load
resistor value.
The system has two poles of importance. One
is due to the compensation capacitor (C3), the
output resistor of error amplifier. The other is
due to the output capacitor and the load resistor.
These poles are located at:
VEA
EA
1P
A3C2
G
f
LOAD
2P
R2C2
1
f
Where, G
EA is the error amplifier
transconductance, 60A/V.
The system has one zero of importance, due to
the compensation capacitor (C3) and the
compensation resistor (R3). This zero is located
at:
3R3C2
1
f
1Z
The system may have another zero of
importance, if the output capacitor has a large
capacitance and/or a high ESR value. The zero,
due to the ESR and capacitance of the output
capacitor, is located at:
ESR
ESR
R2C2
1
f
