IDT8T79S818A-08NLGI REVISION B JULY 11, 2013 2 ©2013 Integrated Device Technology, Inc.
IDT8T79S818I-08 Data Sheet 1-TO-8 DIFFERENTIAL TO UNIVERSAL OUTPUT, CLOCK DIVIDER/FANOUT BUFFER
Pin Description and Characteristic Tables
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See “Table 2. Pin Characteristics” for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1 SCLK Input Pulldown Serial Control Port Mode Data Input. LVCMOS/LVTTL interface levels.
2
MISO
Output Serial Control Port Mode Data Output. LVCMOS/LVTTL interface levels.
3 nRST Input Pullup
Frequency Divider Reset. When the nRST is released (rising edge), the divided
clock outputs are activated and will transition to a high state simultaneously.
See also Timing Diagram. LVCMOS/LVTTL interface levels (“Figure 1. Timing
Diagram”).
4
PCLK
Input Pulldown Non-inverting differential clock input.
5
nPCLK
Input
Pullup /
Pulldown
Inverting differential clock input. V
CC
/ 2 by default when left floating.
6
OE
Input Pulldown
Default output disable. LVCMOS/LVTTL interface levels. See “Table 3B. OE
Truth Table”.
7, 10, 16,
25, 31
V
CC
Power Power supply voltage pin.
8 LE Input Pulldown
Serial Control Port Mode Load Enable. Latches data when the pin gets a high
level. Outputs are disabled when LE is low. LVCMOS/LVTTL interface levels.
9
PWR_SEL
Pulldown Power supply selection. See “Table 3A. PWR_SEL Truth Table”.
11, 12
nQD1, QD1
Output Differential output pair Bank D, output 1. LVPECL or LVDS interface levels.
13, 14
nQD0, QD0
Output Differential output pair Bank D, output 0. LVPECL or LVDS interface levels.
15, 26
V
EE
Power Negative power supply pins.
17, 18
nQC1, QC1
Output Differential output pair Bank C, output 1. LVPECL or LVDS interface levels.
19, 20
nQC0, QC0
Output Differential output pair Bank C, output 0. LVPECL or LVDS interface levels.
21, 22
nQB1, QB1
Output Differential output pair Bank B, output 1. LVPECL or LVDS interface levels.
23, 24
nQB0, QB0
Output Differential output pair Bank B, output 0. LVPECL or LVDS interface levels.
27, 28
nQA1, QA1
Output Differential output pair Bank A, output 1. LVPECL or LVDS interface levels.
29, 30
nQA0, QA0
Output Differential output pair Bank A, output 0. LVPECL or LVDS interface levels.
32
SDATA
Input Pulldown
Serial Control Port Mode Data Input. LVCMOS/LVTTL interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 2pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
R
OUT
Output Impedance MISO
V
CC
= 3.3V 125
V
CC
= 2.5V 145
