IDT8T79S818A-08NLGI REVISION B JULY 11, 2013 19 ©2013 Integrated Device Technology, Inc.
IDT8T79S818I-08 Data Sheet 1-TO-8 DIFFERENTIAL TO UNIVERSAL OUTPUT, CLOCK DIVIDER/FANOUT BUFFER
Termination for 2.5V LVPECL Outputs
Figure 8A and Figure 8B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50
to V
CC
– 2V. For V
CC
= 2.5V, the V
CC
– 2V is very close to ground
level. The R3 in Figure 8B can be eliminated and the termination is
shown in Figure 8C.
Figure 8A. 2.5V LVPECL Driver Termination Example
Figure 8C. 2.5V LVPECL Driver Termination Example
Figure 8B. 2.5V LVPECL Driver Termination Example
2.5V LVPECL Driver
V
CC
= 2.5V
2.5V
2.5V
50Ω
50Ω
R1
250
Ω
R3
250
Ω
R2
62.5
Ω
R4
62.5
Ω
+
2.5V LVPECL Driver
V
CC
= 2.5V
2.5V
50Ω
50Ω
R1
50
Ω
R2
50
Ω
+
2.5V LVPECL Driver
V
CC
= 2.5V
2.5V
50Ω
50Ω
R1
50
Ω
R2
50
Ω
R3
18
Ω
+
IDT8T79S818A-08NLGI REVISION B JULY 11, 2013 20 ©2013 Integrated Device Technology, Inc.
IDT8T79S818I-08 Data Sheet 1-TO-8 DIFFERENTIAL TO UNIVERSAL OUTPUT, CLOCK DIVIDER/FANOUT BUFFER
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 9. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
Figure 9. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
SOLDERSOLDER
PINPIN EXPOSED HEAT SLUG
PIN PAD PIN PADGROUND PLANE LAND PATTERN
(GROUND PAD)
THERMAL VIA
IDT8T79S818A-08NLGI REVISION B JULY 11, 2013 21 ©2013 Integrated Device Technology, Inc.
IDT8T79S818I-08 Data Sheet 1-TO-8 DIFFERENTIAL TO UNIVERSAL OUTPUT, CLOCK DIVIDER/FANOUT BUFFER
Power Considerations
A forced airflow has to be guaranteed in order to meet the thermal requirements of the part at 3.3V ±5%.
No flow is required at 2.5V ±5%.
Table 6. Minimum recommended air flow conditions
LVDS Power Considerations
This section provides information on power dissipation and junction temperature for the IDT8T79S818I-08. Equations and example calculations
are also provided.
1. Power Dissipation.
The total power dissipation for the IDT8T79S818I-08 is the sum of the core power plus the power dissipated into the load.
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: The maximum I
CC
current at 85°C is 269mA.
Power (core)
MAX
= V
CC_MAX
* I
CC_MAX
= 3.465V * 269mA = 932.1mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming 1m/s air flow
and a multi-layer board, the appropriate value is 42°C/W per Table 7A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.9321W * 42°C/W = 124.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7A. Thermal Resistance
JA
for 32-lead VFQFN Package
Power Supply Voltage (V
CC,
Volts) Minimum Airflow
Minimum Typical Maximum Meters per Second
2.375 2.5 2.625 0
3.135 3.3 3.465 1
JA
by Velocity
Meters per Second 012
Multi-Layer PCB, JEDEC Standard Test Boards 48.9°C/W 42°C/W 39.4°C/W

8T79S818A-08NLGI

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 1:8 Output Clock Buffer and Divider
Lifecycle:
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