OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

8T79S818A-08NLGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
IDT8T79S818A-08NLGI REVISION B JULY 11, 2013 4 ©2013 Integrated Device Technology, Inc.
IDT8T79S818I-08 Data Sheet 1-TO-8 DIFFERENTIAL TO UNIVERSAL OUTPUT, CLOCK DIVIDER/FANOUT BUFFER
Output Type Control and Start-up Status
Two output types are available: LVDS and LVPECL. The part features
four modes of output type controls, see Table 3C.
Disabled outputs are in static Low/High
LVDS mode. At start-up, all
outputs are disabled (i.e. in static Low/High LVDS mode) until the part
has been configured. A global hardware Output Enable (OE pin #6)
enables or disables all outputs at once. The global hardware OE has
priority over serial interface configuration.
Table 3C. Output Type Control
Frequency Divider
Each output bank can be individually set to output an integer division
of the input frequency. Factors of 1, 2, 3, 4, 5, 6 and 8 are available
and are programmed by a serial interface.
The nRST pin resets the dividers. When the nRST pin is released, all
output dividers are activated and will transition to a high state
simultaneously.
QXn (/ 1)
QXn (/ 2)
QXn (/ 3)
QXn (/ 4)
QXn (/ 5)
QXn (/ 6)
QXn (/ 8)
Figure 1. Timing Diagram
Control Bits
Output ConfigurationD2 D1
LOW LOW 8 LVDS outputs
HIGH HIGH 8 LVPECL outputs
HIGH LOW
2 LVDS (QAx) +
6 LVPECL (QBx, QCx, QDx) outputs
LOW HIGH
2 LVPECL (QAx) +
6 LVDS (QBx, QCx, QDx) outputs
IDT8T79S818A-08NLGI REVISION B JULY 11, 2013 5 ©2013 Integrated Device Technology, Inc.
IDT8T79S818I-08 Data Sheet 1-TO-8 DIFFERENTIAL TO UNIVERSAL OUTPUT, CLOCK DIVIDER/FANOUT BUFFER
Serial Interface
Configuration of the IDT8T79S818I-08 is achieved by writing 22
configuration bits over serial interface. All 22 bits have to be written in
sequence.
After writing the 22 configuration bits, the LE pin must remain at high
level for outputs to toggle.
D22 D21 D3 D2 D1MISO
D22 D21 D3 D2 D1
SCLK
SDATA
LE
t
SL
t
S
t
H
t
HE
t
HI
t
LO
t
DELAY
t
SH
Figure 2. Serial Interface Timing Diagram for Write and Read Access
Table 3D. Timing AC Characteristics
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
t
S
Data to Clock Setup Time 10 ns
t
H
Data to Clock Hold Time 10 ns
t
HE
Clock to LE Hold Time 10 ns
t
HI
Clock High Duration 25 ns
t
LO
Clock Low Duration 25 ns
t
SL
LE to Clock Setup Time 10 ns
t
SH
LE to SCLK Setup Time 10 ns
t
DELAY
Clock to MISO Delay Time 10 ns
IDT8T79S818A-08NLGI REVISION B JULY 11, 2013 6 ©2013 Integrated Device Technology, Inc.
IDT8T79S818I-08 Data Sheet 1-TO-8 DIFFERENTIAL TO UNIVERSAL OUTPUT, CLOCK DIVIDER/FANOUT BUFFER
Table 3E. Configuration Table
Table 3F. Divider Setting Truth Table
Bit Name Function Truth Table
D22 sd0 Output Bank D, Divider Factor Setting bit 0
See “Table 3F. Divider Setting
Truth Table”
D21 sd1 Output Bank D, Divider Factor Setting bit 1
D20 sd2 Output Bank D, Divider Factor Setting bit 2
D19 sc0 Output Bank C, Divider Factor Setting bit 0
D18 sc1 Output Bank C, Divider Factor Setting bit 1
D17 sc2 Output Bank C, Divider Factor Setting bit 2
D16 sb0 Output Bank B, Divider Factor Setting bit 0
D15 sb1 Output Bank B, Divider Factor Setting bit 1
D14 sb2 Output Bank B, Divider Factor Setting bit 2
D13 sa0 Output Bank A, Divider Factor Setting bit 0
D12 sa1 Output Bank A, Divider Factor Setting bit 1
D11 sa2 Output Bank A, Divider Factor Setting bit 2
D10 oed1 Output Enable QD1
Low: Disabled
High: Enabled
D9 oed0 Output Enable QD0
D8 oec1 Output Enable QC1
D7 oec0 Output Enable QC0
D6 oeb1 Output Enable QB1
D5 oeb0 Output Enable QB0
D4 oea1 Output Enable QA1
D3 oea0 Output Enable QA0
D2 ot1 Banks QB, QC, QD Output Type
Low: LVDS
High: LVPECL
D1 ot0 Bank QA Output Type
sd2
sc2
sb2
sa2
sd1
sc1
sb1
sa1
sd0
sc0
sb0
sa0 Divide Ratio
LLL 1
LLH 2
LHL 3
LHH 4
HLL 5
HLH 6
H H L Reserved
HHH 8
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

8T79S818A-08NLGI

Mfr. #:
Buy 8T79S818A-08NLGI
Manufacturer:
IDT
Description:
Clock Buffer 1:8 Output Clock Buffer and Divider
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet