12
Notes:
1. Output IC power dissipation is derated linearly above 100°C from 580 mW to 260 mW at 125°C.
2. This supply is optional. Required only when negative gate drive is implemented.
3. Maximum pulse width = 1 μs, maximum duty cycle = 1%.
4. Maximum 500 ns pulse width if peak V
DESAT
> 10 V.
5. 15V is the recommended minimum operating positive supply voltage (V
CC2
– V
E
) to ensure adequate margin in excess of the maximum V
UVLO+
threshold of 13.5V.
6. For High-Level Output Voltage testing, V
OH
is measured with a DC-load current. When driving capacitive loads, V
OH
approaches V
CC
as I
OH
approaches zero.
7. Maximum pulse width = 1.0 ms, maximum duty cycle = 20%.
8. Once V
OUT
of the ACPL-344JT is allowed to go high (V
CC2
– V
E
> V
UVLO
), the DESAT detection feature of the ACPL-344JT will be the primary source
of IGBT protection. UVLO is required to ensure DESAT is functional. Once V
CC2
exceeds V
UVLO+
threshold, DESAT remains functional until V
CC2
is below the V
UVLO-
threshold. Thus, the DESAT detection and UVLO features of the ACPL-344JT work in conjunction to ensure constant IGBT
protection.
9. t
PLH
is dened as the propagation delay from 50% of LED input I
F
to 50% of High-level output.
10. t
PHL
is dened as the propagation delay from 50% of LED input I
F
to 50% of Low-level output.
11. Pulse Width Distortion (PWD) is dened as (t
PHL
– t
PLH
) of any given unit.
12. As measured from I
F
to V
O
.
13. Dead Time Distortion (DTD) is dened as (t
PLH
– t
PHL
) between any two ACPL-344JT parts under the same test conditions.
14. Common-mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common-mode pulse, V
CM
, to assure that the
output remains in a high state (meaning V
O
> 15V).
15. Common-mode transient immunity in the low state is the maximum tolerable dV
CM
/dt of the common-mode pulse, V
CM
, to assure that the
output remains in a low state (meaning V
O
< 1.0V).
16. The “increasing” (meaning turn-on or “positive going” direction) of V
CC2
– V
E
.
17. The “decreasing” (meaning turn-o or “negative going” direction) of V
CC2
– V
E
.
18. The delay time when V
CC2
exceeds UVLO+ threshold to UVLO High – 50% of UVLO positive-going edge.
19. The delay time when V
CC2
falls below UVLO– threshold to UVLO Low – 50% of UVLO negative-going edge.
20. The delay time when V
CC2
exceeds UVLO+ threshold to 50% of High-level output.
21. The delay time when V
CC2
falls below UVLO– threshold to 50% of Low-level output.
22. The delay time for ACPL-344JT to respond to a DESAT fault condition without any external DESAT capacitor.
23. The amount of time from when DESAT threshold is exceeded to 90% of V
GATE
at mentioned test conditions.
24. The amount of time from when DESAT threshold is exceeded to 10% of V
GATE
at mentioned test conditions.
25. The amount of time from when DESAT threshold is exceeded to FAULT output Low – 50% of V
CC1
voltage.
26. The amount of time when DESAT threshold is exceeded, Output is mute to LED input.
27. The amount of time when DESAT Mute time is expired, LED input must be kept LOW for Fault status to return to HIGH.
28. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥6000V
RMS
for 1 second.
29. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous-
voltage rating. For the continuous-voltage rating, refer to your equipment level safety specication or IEC/EN/DIN EN 60747-5-5 Insulation
Characteristics Table.
30. Device considered a two-terminal device: pins 1 through 8 are shorted together and pins 9 through 16 are shorted together.
