Table 3: LPDDR2 Ball Descriptions
Symbol Type Description
CA[9:0] Input Command/address inputs: Provide the command and address inputs according to
the command truth table.
CK, CK# Input Clock: CK and CK# are differential clock inputs. All CA inputs are sampled on
both the positive and negative edge of CK. CS and CKE inputs are sampled at
the positive edge of CK. AC timings are referenced to clock.
DM[1:0] Input Data mask:DM is an input mask signal for write data. Although DM balls are in-
put-only, the DM loading is designed to match that of DQ and DQS balls.
DM[1:0] is DM for each of the two data bytes, respectively.
DQ[15:0] Input/
output
Data bus: Data inputs/outputs.
DQS[3:0]
DQS#[3:0]
Input/
output
Data strobe: Coordinates READ/WRITE transfers of data; one DQS/DQS# pair per
DQ byte.
V
DD1
Supply V
DD1
: LPDDR2 power supply 1.
V
DD2
Supply V
DD2
: LPDDR2 power supply 2.
V
DDCA
Supply V
DDCA
: LPDDR2 CA power supply.
V
DDQ
Supply V
DDQ
: LPDDR2 I/O power supply.
V
REFCA
Supply V
REFCA
: LPDDR2 reference for CA pins.
V
REFDQ
Supply V
REFDQ
: LPDDR2 reference for DQ pins.
V
SSCA
Supply V
SSCA
: LPDDR2 I/O ground.
V
SSQ
Supply V
SSQ
: LPDDR2 I/O ground.
V
SS
Supply V
SS
: Shared ground.
ZQ Input External impedance (240-Ohm): This signal is used to calibrate the device output
impedance.
Table 4: Non-Device-Specific Descriptions
Symbol Type Description
DNU – Do not use: Must be grounded or left floating.
NC – No connect: Not internally connected.
Product Brief – 121-Ball LPDDR2-PCM and LPDDR2 MCP
Ball Assignments and Descriptions
PDF: 09005aef84e25954
121ball_pcm_lpddr2_product_brief.pdf – Rev. B 12/12 EN
6
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
