Phase Change Memory General Description
PCM is a new class of nonvolatile memory devices that stores information through a re-
versible structural phase change in a chalcogenide material. The material exhibits a
change in both electrical and optical properties when changed from the amorphous
(disordered) to the polycrystalline (regularly ordered) state. The amorphous state corre-
sponds to the reset state (0); the polycrystalline state corresponds to the set state (1). In
PCM, information is stored during the change in resistance the chalcogenide material
undergoes during a phase change
The device uses a DDR architecture on the command/address (CA) bus to reduce the
number of input pins in the system. The 10-bit CA bus contains command, address, and
row buffer information. Each command uses one clock cycle, during which command
information is transferred on both the positive and negative edge of the clock. The de-
vice also uses a DDR architecture on the DQ pins to achieve high-speed operation.
The LPDDR2-PCM device uses a complete set of commands that are compatible with
the JEDEC industry-standard specification No. JESD209-2E.
The DDR architecture is essentially a 4n-prefetch architecture with an interface de-
signed to transfer two data bits per DQ every clock cycle at the I/O pins. A single read or
write access effectively consists of a single, 4n-bit wide, one-clock-cycle data transfer at
the internal core and four corresponding, n-bit wide, one-half-clock-cycle data trans-
fers at the I/O pins.
The device is organized into four RABs and RDBs, 32 bytes each. Read or write accesses
to device are performed issuing a sequence of PREACTIVE commands to deliver part of
the row address to one of four RABs in the device; ACTIVATE commands to fill one of
the four RDBs in the device; and READ or WRITE commands.
Operations other than array reads are performed by accessing an overlay window that is
mapped over the array space of the memory. The overlay window base address is pro-
grammed using the mode registers.
The device can be erased electrically at block level and programmed in-system on a
word-by-word basis using a V
DD1
supply for the circuitry and V
DDQ
supply for the I/O
pins. An optional V
ACC
power supply is provided for factory programming.
A multiple partition architecture allows dual operations: While writing or erasing in one
partition, READ operations are possible in other partitions. Only one partition at a time
can be in write or erase mode.
Erase can be suspended to perform a WRITE or READ operation in any other block ex-
cept for the one being erased, and then resumed. Writing can be suspended to read data
at any memory location except the one being modified, and then resumed.
To issue embedded commands like PROGRAM or ERASE, the operation code and data
are written to the overlay window of the memory. An internal program/erase controller
manages the timings necessary for embedded operations. The end of a WRITE or
ERASE operation can be detected and any error conditions identified in the status regis-
ter. The command set required to control the memory is consistent with the JEDEC
standard.
Read and write accesses to the device are burst oriented at different frequencies using a
differential clock up to 400 MHz. Accesses start at a selected location and continue for a
configured number of locations.
Product Brief – 121-Ball LPDDR2-PCM and LPDDR2 MCP
Phase Change Memory General Description
PDF: 09005aef84e25954
121ball_pcm_lpddr2_product_brief.pdf – Rev. B 12/12 EN
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© 2012 Micron Technology, Inc. All rights reserved.
