ADM1034ARQ-REEL7 Datasheet ADM1034ARQZ-REEL, ADM1034ARQ-REEL, ADM1034ARQ-REEL7 | P10-P12

ADM1034

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Table 6. RESISTOR RATIOS FOR SETTING LOCATION BITS

Ideal Ratio R2/(R1 + R2)

R1 kW R2 W

Actual R2/(R1 + R2) Error %

SMBus Ver

(Note 1)

SMBus Address UDID LLL

N/A 0 O/C 1 0 ARP N/A 111

0.8125 18 82 0.82 +0.75 ARP N/A 110

0.6875 22 47 0.6812 −0.63 ARP N/A 101

0.5625 12 15 0.5556 −0.69 ARP N/A 100

0.4375 15 12 0.4444 +0.69 FD 0x53 N/A

0.3125 47 22 0.3188 +0.63 FD 0x52 N/A

0.1875 82 18 0.18 −0.75 FD 0x51 N/A

N/A O/C 0 0 0 FD 0x50 N/A

1. ARP denotes ARP-capable mode, FD denotes fixed and discoverable mode.

Table 7. UDID VALUES

Bit No. Name Function Value

<127:120> Device Capabilities Describes the ADM1034’s capabilities (for instance, that it supports

PEC and uses a random number address device).

11000001

<119:112> Version/Revision UDID version number (Version 1) and silicon revision identification 00001010

<111:96> Vendor ID Analog Devices vendor ID number, as assigned by the SBS

Implementer’s Forum or the PCI SIG.

00010001

11010100

<95:80> Device ID Device ID. 00010000

00110100

<79:64> Interface Identifies the protocol layer interfaces supported by the ADM1034.

This represents SMBus 2.0 as the Interface version..

00000000

00000100

<63:48> Subsystem Vendor ID Subsystem Vendor ID = 0 (subsystem fields are unsupported). 00000000

00000000

<47:32> Subsystem Device ID Subsystem Device ID = 0 (subsystem fields are unsupported). 00000000

00000000

<31:0> Vendor Specific ID A unique number per device. Contains LOCATION information (LL)

and a 16-bit random number (x). See Table 9 for information on

setting the LLL bits.

00000000

00000LLL

xxxxxxxx

SMBus 2.0 Fixed and Discoverable Mode

The ADM1034 also supports fixed and discoverable

mode, which is backwards compatible with SMBus 1.0 and

1.1. Fixed and discoverable mode supports all the same

functionality as ARP-capable mode, except for assign

address in which case it powers up with a fixed address and

is not changed by the assign address call. The fixed address

is determined by the state of the LOCATION pin on

powerup.

SMBus 2.0 Read and Write Operations

The master initiates data transfer by establishing a start

condition, defined as a high-to-low transition on the serial

data line (SDA) while the serial clock line (SCL) remains

high. This indicates that an address/data stream is to follow.

All slave peripherals connected to the serial bus respond to

the start condition and shift in the next 8 bits, which consist

of a 7-bit address (MSB first) plus an R/W

bit. This last bit

determines the direction of the data transfer (whether data is

written to or read from the slave device).

1. The peripheral that corresponds to the transmitted

address responds by pulling the data line low

during the low period before the 9th clock pulse,

which is known as the acknowledge bit. All other

devices on the bus remain idle while the selected

device waits for data to be read from or written to

it. If the R/W

bit is a 0, the master writes to the

slave device. If the R/W

bit is a 1, the master reads

from it.

2. Data is sent over the serial bus in sequences of 9

clock pulses − 8 bits of data followed by an

acknowledge bit from the slave device. Transitions

on the data line must occur during the low period

of the clock signal and remain stable during the

high period, because a low-to-high transition when

the clock is high may be interpreted as a stop

signal. The number of data bytes that can be

transmitted over the serial bus in a single read or

write operation is limited only by what the master

and slave devices can handle.

3. When all data bytes have been read or written,

stop conditions are established. In write mode, the

master pulls the data line high during the 10th

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clock pulse to assert a stop condition. In read

mode, the master device overrides the

acknowledge bit by pulling the data line high

during the low period before the 9th clock pulse.

This is known as no acknowledge. The master

takes the data line low during the low period

before the 10th clock pulse, then high during the

10th clock pulse to assert a stop condition.

It is not possible to mix read and write in one operation,

because the type of operation is determined at the beginning

and cannot be changed without starting a new operation.

To write data to one of the device data registers or to read

data from it, the address pointer register (APR) must be set

so that the correct data register is addressed; then data can be

written into that register or read from it. The first byte of a

write operation always contains an address that is stored in

the APR. If data is to be written to the device, then the write

operation contains a second data byte, which is written to the

As illustrated in Figure 17, the device address is sent over

the bus, followed by R/W

set to 0. This is followed by two

data bytes. The first data byte is the address of the internal

data register to be written to, which is stored in the APR. The

second data byte is the data to be written to the internal data

When reading data from a register there are two

possibilities.

If the ADM1034’s APR value is unknown or incorrect, it

must be set to the correct value before data can be read from

the desired data register. To do this, perform a write to the

ADM1034 as before, but send only the data byte containing

the register. (See Figure 18.) A read operation is then

performed, using the serial bus address and the R/W

bit set

to 1, followed by the data byte read from the data register.

(See Figure 19.)

However, if the APR is already at the desired address, data

can be read from the corresponding data register without

first writing to the APR. In this case, Figure 18 can be

omitted.

In Figure 17 to Figure 19, the serial bus address is

determined by the state of the LOCATION pin on powerup.

Figure 17. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register

R/W

SCL

SDA

ACK. BY

ADM1034

START BY

MASTER

191

ACK. BY

ADM1034

ACK. BY

ADM1034

STOP BY

MASTER

SCL (CONTINUED)

SDA (CONTINUED)

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

ADDRESS POINTER REGISTER BYTE

FRAME 3

DATA BYTE

A3A4A5A6

Figure 18. Writing to the Address Pointer Register Only (Send Byte)

SCL

SDA

ACK. BY

ADM1034

START BY

MASTER

ACK. BY

ADM1034

STOP BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

ADDRESS POINTER REGISTER BYTE

R/W

A3A4A5A6

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Figure 19. Reading Data from a Previously Selected Register

SCL

SDA

NO ACK. BY

ADM1034

START BY

MASTER

ACK. BY

ADM1034

STOP BY

MASTER

A1 A0

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

DATA BYTE FROM ADM1034

R/W

A3A4A5A6

The ADM1034 supports single byte as well as block read

and write operations. The register address determines

whether a single byte or multiple byte (block) operation is

run. For a single byte operation, the MSB of the register

address is set to 0; for a multiple byte operation, it is set to 1.

The number of bytes read in a multiple byte operation is set

in the #Bytes/Block Read Register at Address 0x00. The

number of bytes written to the ADM1034 is specified during

the block write operation. The addresses quoted in the

byte operation. For multiple byte operations, set the MSB of

each register address to 1.

Write Operations

The SMBus specifications define protocols for read and

write operations. The ADM1034 supports send byte, write

byte, and block byte SMBus write protocols. The following

abbreviations are used in the diagrams:

S − START

P − STOP

R − READ

W − WRITE

A − ACKNOWLEDGE

− NO ACKNOWLEDGE

Send Byte

In this operation, the master device sends a

single-command byte to a slave device as follows:

1. The master device asserts a start condition on

SDA.

2. The master sends a 7-bit address followed by the

write bit (low).

3. The addressed slave device asserts ACK on SDA.

4. The master sends the register address.

5. The slave asserts ACK on SDA.

6. The master asserts a stop condition on SDA, and

the transaction ends.

Figure 20. Send Byte

SLAVE

ADDRESS

REG

ADDRESS

W A A P

The ADM1034 uses the send byte operation to write a

same address. (See Figure 24). The user may be required to

read data from the register immediately after setting up the

address. If so, the master can assert a repeat start condition

immediately after the final ACK and carry out a single byte

read without asserting an intermediate stop condition.

Write Byte

In this operation, the master device sends a register

address and one data byte to the slave device as follows:

1. The master asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed

by a write bit (low).

3. The addressed slave device asserts ACK on SDA.

4. The master sends the register address. The MSB of

the register address should equal 0 for a write byte

operation. If the MSB equals 1, a block write

operation takes place.

5. The slave asserts ACK on SDA.

6. The master sends a data byte.

7. The slave asserts ACK on SDA.

8. The master asserts a stop condition on SDA to end

the transaction.

Figure 21. Write Byte Operation

SLAVE

ADDRESS

REG

ADDRESS

DATAW A AA P

Block Write

In this operation, the master device writes a block of data

to a slave address as follows. A maximum of 32 bytes can be

written.

1. The master asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed

by a write bit (low).

3. The addressed slave device asserts ACK on SDA.

4. The master sends the register address. The register

address sets up the address pointer register and

determines whether a block write (MSB = 1) or a

byte write (MSB = 0) takes place.

5. The slave asserts ACK on SDA.

6. The master sends the byte count.

7. The slave asserts ACK on SDA.

8. The master sends N data bytes.

9. The slave asserts ACK on SDA after each byte.

10. The master asserts a stop condition on SDA to end

the transaction.

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ADM1034ARQ-REEL7

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