CAT15008, CAT15016
http://onsemi.com
5
PIN DESCRIPTION
RESET/RESET
: Reset output is available in two versions:
CMOS Active Low (CAT150xx9) and CMOS Active High
(CAT150xx1). Both versions are push−pull outputs for high
efficiency.
SI: The serial data input pin accepts op−codes, addresses and
data. In SPI modes (0,0) and (1,1) input data is latched on the
rising edge of the SCK clock input.
SO: The serial data output pin is used to transfer data out of
the device. In SPI modes (0,0) and (1,1) data is shifted out
on the falling edge of the SCK clock.
SCK: The serial clock input pin accepts the clock provided
by the host and used for synchronizing communication
between host and CAT15008/16.
CS
: The chip select input pin is used to enable/disable the
CAT15008/16. When CS
is high, the SO output is tri−stated
(high impedance) and the device is in Standby Mode (unless
an internal write operation is in progress). Every
communication session between host and CAT15008/16
must be preceded by a high to low transition and concluded
with a low to high transition of the CS input.
WP: The write protect input pin will allow all write
operations to the device when held high. When WP
pin is
tied low and the WPEN bit in the Status Register (refer to
Status Register description, later in this Data Sheet) is set to
“1”, writing to the Status Register is disabled.
DEVICE OPERATION
The CAT15008/16 products combine the accurate voltage
monitoring capabilities of a standalone voltage supervisor
with the high quality and reliability of standard EEPROMs
from ON Semiconductor.
RESET CONTROLLER DESCRIPTION
The reset signal is asserted LOW for the CAT150xx9 and
HIGH for the CAT150xx1 when the power supply voltage
falls below the threshold trip voltage and remains asserted
for at least 140 ms (t
PURST
) after the power supply voltage
has risen above the threshold. Reset output timing is shown
in Figure 2.
The CAT15008/16 devices protect mPs against brown−out
failure. Short duration V
CC
transients of 4 msec or less and
100 mV amplitude typically do not generate a Reset pulse.
Figure 1 shows the maximum pulse duration of
negative−going V
CC
transients that do not cause a reset
condition. As the amplitude of the transient goes further
below the threshold (increasing V
TH
− V
CC
), the maximum
pulse duration decreases. In this test, the V
CC
starts from an
initial voltage of 0.5 V above the threshold and drops below
it by the amplitude of the overdrive voltage (V
TH
− V
CC
).
Figure 1. Maximum Transient Duration without
Causing a Reset Pulse vs. Overdrive Voltage
TRANSIENT DURATION [μs]
RESET OVERDRIVE V
TH
- V
CC
[mV]
T
AMB
= 25ºC
CAT150xxM
CAT150xxZ
