CAT15008, CAT15016
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8
WRITE OPERATIONS
The CAT15008/16 device powers up into a write disable
state. The device contains a Write Enable Latch (WEL)
which must be set before attempting to write to the memory
array or to the status register. In addition, the address of the
memory location(s) to be written must be outside the
protected area, as defined by BP0 and BP1 bits from the
status register.
Write Enable and Write Disable
The internal Write Enable Latch and the corresponding
Status Register WEL bit are set by sending the WREN
instruction to the CAT15008/16. Care must be taken to take
the CS
input high after the WREN instruction, as otherwise
the Write Enable Latch will not be properly set. WREN
timing is illustrated in Figure 4. The WREN instruction must
be sent prior any WRITE or WRSR instruction.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 5. Disabling write
operations by resetting the WEL bit, will protect the device
against inadvertent writes.
Figure 4. WREN Timing
SCK
SI
CS
SO
0
1
HIGH IMPEDANCE
1
00 000
Note: Dashed Line = mode (1, 1)−−−−−
Figure 5. WRDI Timing
SCK
SI
CS
SO
0
1
HIGH IMPEDANCE
00 000
Note: Dashed Line = mode (1, 1)−−−−−
0
Byte Write
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 16−bit address
and data as shown in Figure 6. Only 10 significant address
bits are used by the CAT15008 and 11 by the CAT15016. The
rest are don’t care bits, as shown in Table 11. Internal
programming will start after the low to high CS
transition.
During an internal write cycle, all commands, except for
RDSR (Read Status Register) will be ignored. The RDY
bit
will indicate if the internal write cycle is in progress
(RDY
high), or the device is ready to accept commands
(RDY
low).
Page Write
After sending the first data byte to the CAT15008/16, the
host may continue sending data, up to a total of 32 bytes,
according to timing shown in Figure 7. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
page, thus possibly overwriting previously loaded data.
Following completion of the write cycle, the CAT15008/16
is automatically returned to the write disable state.
