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HCPL-2503#500

P1-P3P4-P6P7-P9P10-P12
10
Figure 2. Input current vs. forward voltageFigure 1. Current transfer ratio vs. input current Figure 3. Current transfer ratio vs. temperature
Figure 5. Logic high output current vs. temperatureFigure 4. Propagation delay vs. temperature
Figure 6. Switching test circuit
HCPL-2503 fig 2
V
F
– FORWARD VOLTAGE – VOLTS
100
10
0.1
0.01
1.10 1.20 1.30 1.40
I
F
– FORWARD CURRENT – mA
1.50
1.0
0.001
1000
I
F
V
F
+
T
A
= 25°C
–
HCPL-2503 fig 3
1.2
0.8
0.6
0.2
0
-60 -20
NORMALIZED CURRENT TRANSFER RATIO
T
A
– TEMPERATURE – °C
-40 20 40 80 100
V
O
= 0.5 V
V
CC
= 5.0 V
1.0
0.4
I
F
= 8 mA
I
F
= 16 mA
NORMALIZED TO T
A
= 25°C
0 60
HCPL-2503 fig 4
2.0
1.0
0
-60 -20
t
P
– PROPAGATION DELAY – µs
T
A
– TEMPERATURE – °C
-40 20 40 80 100
I
F
= 8 mA
R
L
= 7.5 kΩ
1.5
0.5
0 60
I
F
= 16 mA
R
L
= 4.7 kΩ
V
CC
= 5.0 V
t
PHL
t
PLH
HCPL-2503 fig 5
10
1
0 30
I
OH
– OUTPUT CURRENT – nA
T
A
– TEMPERATURE – °C
10 50 70 100 110
100
40 8020 60 90
HCPL-2503 fig 6
V
O
HP 8007
PULSE
GEN.
Z
O
= 50 Ω
t
r
= 5 ns
I
F
MONITOR
I
F
R
L
C
L
= 15 pF
100 Ω
0
t
PHL
t
PLH
V
O
I
F
V
OL
1.3 V 1.3 V
5 V
+5 V
10% DUTY CYCLE
1/f 500 µs
81
72
63
54
HCPL-2503 fig 1
1.4
1.2
0.8
0.6
0.2
0
0 8
NORMALIZED CURRENT TRANSFER RATIO
I
F
– INPUT CURRENT – mA
4 12 16 20 24
V
O
= 0.5 V
V
CC
= 5.0 V
T
A
= 25°C
NORMALIZED TO
I
F
= 8 mA
I
F
= 16 mA
1.0
0.4
Figure 7. Test circuit for transient immunity and typical waveforms
Figure 8. Recommended circuits
Recommended Operation
The HCPL-2503 optocoupler is specied for use in LSTTL-
to-LSTTL and TTL-to-LSTTL interfaces. The recommended
circuits show the interface design and give suggested
component values. The input current I
F
is given as both
a nominal value and a range. The range in I
F
results
from the tolerances in V
CC
and the input resistor R
IN
.
The CTR of the optocoupler is given as the minimum
HCPL-2503 fig 8
I
O
R
IN
R
L
81
72
63
54
V
CC2
V
CC1
I
F
HCPL-2503
7404
74LS04
7405
74LS05
74LS04
74LS05
A B
A) TYPICAL NON-INVERTING CIRCUIT
I
O
R
IN
R
L
81
72
63
54
V
CC2
V
CC1
I
F
HCPL-2503
7405
74LS05
74LS04
74LS05
A
B
B) TYPICAL INVERTING CIRCUIT
(SEE NOTE 10)
HCPL-2503 fig 7
V
O
I
F
R
L
A
HP 8007
PULSE GEN.
V
CM
+
V
FF
V
O
V
OL
V
O
0 V
10%
90% 10%
90%
SWITCH AT A: I = 0 mA
F
SWITCH AT B: I = 16 mA
F
V
CM
t
r
t
f
5 V
+5 V
–
10 V
t
r
, t
f
= 8 ns
81
72
63
54
B
initial value over temperature, taken directly from the
Electrical Specications. The value given for I
OL
(min) is
based on the minimum CTR and the minimum I
F
using
worst case values for R
L
and V
CC
. The resulting I
OL
(min)
has ample design margin, allowing more than 20% for
CTR degradation even under these worst case condi-
tions. For additional information on CTR degradation
see Application Note 1002.
Recommended Circuit Design Parameters
LSTTL-to- TTL-to-
Parameter Symbol LSTTL LSTTL Units Comments Fig. Note
Input
Logic Low Output V
OL
(A) 0.5 0.4 V Maximum
Voltage – Input Gate
Supply Voltage – Input V
CC1
5.0 5.0 V ± 5%
Input Resistor R
IN
360 180 Ω ± 5% 8a
430 200 8b
Input Current I
F
8 16 mA Nominal
Input Current Range I
F
6.75–10 14.0–20 mA 8a
14.5–20 8b
Output
Logic Low Output V
OL
(B) 0.5 0.5 V Maximum
Voltage – HCPL-2503
Supply Voltage – Output V
CC2
5.0 5.0 V ± 5%
Pull-Up Resistor R
L
20 8.2 kΩ ± 5% 11
Required Current Sink I
OL
0.61 1.0 mA Worst Case V
CC
, 12
for Logic Low (max) R
L
, I
IL
(B)
HCPL-2503 Current CTR 11 9 % Minimum T
A
= 0˚C to
Transfer Ratio +70°C
Logic Low Output I
OL
0.74 1.26 mA Worst Case V
CC
, CTR, I
F
8a 13
Current – HCPL-2503
(min)
1.30
T
A
= 0
°
C to +70
°
C
8b
Data Rate f
D
250 250 kb/s NRZ, T
A
= 25°C 14
For product information and a complete list of distributors, please go to our website: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved.
AV02-0520EN - June 15, 2007
Notes:
10. The inverting circuit has higher power consumption and must use open collector gates on the input.
11. The load resistor R
L
must be large enough to guarantee logic LOW and small enough to guarantee logic HIGH under worst case conditions:
V
CC
(max) – V
OL
V
CC
(min) – V
IH
(B)
I
OL
(2503) – I
IL
(B) I
OH
(2503) – I
IH
(B)
The selection of R
L
is the same for both inverting and non-inverting circuits.
12. The maximum current sink required for logic LOW is:
I
OL
(max) = I
IL
(B) (max) + I
R
(max)
where I
R
is the current through R
L
.
13. The ratio of I
OL
(min) to I
OL
(max) gives the design margin for CTR degradation. See Application Note 1002.
14. The maximum data rate is dened as:
1
f
D
= bits/second NRZ
t
PHL
+ t
PLH
≤ R
L
≤
P1-P3P4-P6P7-P9P10-P12

HCPL-2503#500

Mfr. #:
Buy HCPL-2503#500
Manufacturer:
Broadcom / Avago
Description:
High Speed Optocouplers 1MBd 1Ch 25mA
Lifecycle:
New from this manufacturer.
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