6.42
3
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Symbol Pin Function I/O Active Description
A
0
–A
14
Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination
of the rising edge of CLK and ADSC Low or ADSP Low and CE Low.
ADSC
Address Status
(Cache Controller)
I LOW Synchronous Address Status from Cache Controller. ADSC is an active LOW
input that is used to load the address registers with new addresses. ADSC is
NOT GATED by CE.
ADSP
Address Status
(Processor)
I LOW Synchronous Address Status from Processor. ADSP is an active LOW input that is
used to load the address registers with new addresses. ADSP is gated by CE.
ADV
Burst Address Advance I LOW Synchronous Address Advance. AD V is an active LOW input that is used to
advance the internal burst counter, controlling burst access after the initial
address is loaded. When this input is HIGH the burst counter is not incremented;
that is, there is no address advance.
BWE
Byte Write Enable I LOW Synchronous byte write enable gates the byte write inputs BW
1
–BW
4
. If BWE is
LOW at the rising edge of CLK then BW
X
inputs are passed to the next stage in
the circuit. A byte write can still be blocked if ADSP is LOW at the rising edge of
CLK. If ADSP is HIGH and BW
X
is LOW at the rising edge of CLK then data will
be written to the SRAM. If BWE is HIGH then the byte write inputs are blocked
and only GW can initiate a write cycle.
BW
1
- BW
4
Individual Byte
Write Enables
I LOW Synchronous byte write enables. BW
1
controls I/O(7:0), BW
2
controls I/O(15:8),
etc. Any active byte write causes all outputs to be disabled. ADSP LOW
disables all byte writes. BW
1
–BW
4
must meet specified setup and hold times
with respect to CLK.
CE
Chip Enable I LOW Synchronous chip enable. CE is used with CS
0
and CS
1
to enable the
IDT71V432. CE also gates ADSP.
CLK Clock I N/A This is the clock input to the IDT71V432. All timing referenc es for the device are
made with respect to this input.
CS
0
Chip Select 0 I HIGH Synchronous active HIGH chip select. CS
0
is used with CE and CS
1
to enable
the chip.
CS
1
Chip Select 1 I LOW Synchronous active LOW chip select. CS
1
is used with CE and CS
0
to enable
the chip.
GW
Global Write Enable I LOW
Synchronous global write enable. This input will write all four 8-bit data bytes
when LOW on the rising edge of CLK. GW supercedes individual byte write
enables.
I/O
0
–I/O
31
Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. Both the data input path and data output
path are registered and triggered by the rising edge of CLK.
LBO
Linear Burst Order I LOW Asynchronous burst order selection DC input. When LBO is HIGH the Interleaved
(Intel) burst sequence is selected. When LBO is LOW the Linear (PowerPC) burst
sequence is selected. LBO is a static DC input and must not change state while
the device is operating.
OE
Output Enable I LOW Asynchronous output enable. When OE is LOW the data output drivers are
enabled on the I/O pins. OE is gated internally by a delay circuit driven by CE,
CS
0
, and CS
1
. In dual-bank mode, when the user is utilizing two banks of
IDT71V432 and toggling back and forth between them using CE, the internal
delay circuit delays the OE activation of the data output drivers by one cycle to
prevent bus contention between the banks. When used in single bank mode CE,
CS
0
, and CS
1
are all tied active and there is no output enable delay. When OE is
HIGH the I/O pins are in a high-impedence state.
V
DD
Power Supply N/A N/A 3.3V power supply inputs.
V
SS
Ground N/A N/A Ground pins.
ZZ Sleep Mode I HIGH Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power
down the IDT71V432 to its lowest power consumption level. Data retention is
guaranteed in Sleep Mode.
3104 tbl 02
Pin Definitions
(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
