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71V432S5PFG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
6.42
4
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 6 pF
C
I/O
I/O Capacitance V
OUT
= 3dV 7 pF
3104 t bl 06
Absolute Maximum Ratings
(1)
Capacitance
(TA = +25°C, f = 1.0MHz, TQFP package)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
DD and Input terminals only.
3. I/O terminals.
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
Symbol Rating Value Unit
V
TERM
(2)
Terminal Voltage with
Respect to GND
–0.5 to +4.6 V
V
TERM
(3)
Terminal Voltage with
Respect to GND
–0.5 to V
DD
+0.5 V
T
A
Operating Temperature 0 to +70
o
C
T
BIAS
Temperature Under Bias –55 to +125
o
C
T
STG
Storage Temperature –55 to +125
o
C
P
T
Power Dissipation 1.0 W
I
OUT
DC Output Current 50 mA
3104 tbl 05
Recommended DC Operating
Conditions
NOTES:
1. VIL (min) = –1.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max) = 6.0V for pulse width less than tCYC/2, once per cycle.
Symbol Parameter Min. Typ. Max. Unit
V
DD
Supply Voltage 3.135 3.3 3.63 V
V
SS
Ground 0 0 0 V
V
IH
Input High Voltage — Inputs 2.0 — 4.6
(2)
V
V
IH
Input High Voltage — I/O 2.0 — V
DD
+0.3 V
V
IL
Input Low Voltage –0.5
(1)
—0.8V
3104 tbl 04
Recommended Operating
Temperature and Supply Voltage
Grade Temperature V
SS
V
DD
Commercial 0°C to +70°C 0V 3.3V+10/-5%
Industrial –40°C to +85°C 0V 3.3V+10/-5%
3104 tbl 03
6.42
5
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Configuration
Top View TQFP
NOTES:
1. Pin 14 can either be directly connected to VDD or not connected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
6
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Synchronous Truth Table
(1,2)
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. ZZ = LOW for this table.
3. OE is an asynchronous input.
Operation
Address
Used
CE
CS
0
CS
1
ADSP ADSC ADV GW BWE BW
X
OE
(3 )
CLK I/O
Deselected Cycle, Power Down None H X X X L X X X X X ↑ Hi-Z
Deselected Cycle, Power Down NoneLXHLXXXXXX
↑
Hi-Z
Deselected Cycle, Power Down NoneLLXLXXXXXX
↑
Hi-Z
Deselected Cycle, Power Down None L X H X L X X X X X ↑ Hi-Z
Deselected Cycle, Power Down None L L X X L X X X X X
↑
Hi-Z
Read Cycle, Begin Burst ExternalLHLLXXXXXL
↑
D
OUT
Read Cycle, Begin Burst ExternalLHLLXXXXXH↑ Hi-Z
Read Cycle, Begin Burst External L H L H L X H H X L ↑ D
OUT
Read Cycle, Begin Burst External L H L H L X H L H L
↑
D
OUT
Read Cycle, Begin Burst External L H L H L X H L H H
↑
Hi-Z
Write Cycle, Begin Burst External L H L H L X H L L X ↑ D
IN
Write Cycle, Begin Burst External L H L H L X L X X X
↑
D
IN
Read Cycle, Continue Burst Next X X X H H L H H X L
↑
D
OUT
Read Cycle, Continue Burst Next X X X H H L H H X H
↑
Hi-Z
Read Cycle, Continue Burst Next X X X H H L H X H L
↑
D
OUT
Read Cycle, Continue Burst Next X X X H H L H X H H
↑
Hi-Z
Read Cycle, Continue Burst Next H X X X H L H H X L
↑
D
OUT
Read Cycle, Continue Burst Next H X X X H L H H X H ↑ Hi-Z
Read Cycle, Continue Burst Next H X X X H L H X H L
↑
D
OUT
Read Cycle, Continue Burst Next H X X X H L H X H H
↑
Hi-Z
Write Cycle, Continue Burst Next X X X H H L H L L X ↑ D
IN
Write Cycle, Continue Burst Next X X X H H L L X X X
↑
D
IN
Write Cycle, Continue Burst Next H X X X H L H L L X
↑
D
IN
Write Cycle, Continue Burst Next H X X X H L L X X X
↑
D
IN
Read Cycle, Suspend Burst CurrentXXXHHHHHXL↑ D
OUT
Read Cycle, Suspend Burst CurrentXXXHHHHHXH
↑
Hi-Z
Read Cycle, Suspend Burst CurrentXXXHHHHXHL
↑
D
OUT
Read Cycle, Suspend Burst CurrentXXXHHHHXHH↑ Hi-Z
Read Cycle, Suspend Burst CurrentHXXXHHHHXL↑ D
OUT
Read Cycle, Suspend Burst CurrentHXXXHHHHXH
↑
Hi-Z
Read Cycle, Suspend Burst Current H X X X H H H X H L
↑
D
OUT
Read Cycle, Suspend Burst Current H X X X H H H X H H ↑ Hi-Z
Write Cycle, Suspend Burst CurrentXXXHHHHLLX
↑
D
IN
Write Cycle, Suspend Burst Current X X X H H H L X X X
↑
D
IN
Write Cycle, Suspend Burst Current H X X X H H H L L X ↑ D
IN
Write Cycle, Suspend Burst Current H X X X H H L X X X ↑ D
IN
3104 tbl 07
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

71V432S5PFG

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Buy 71V432S5PFG
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Description:
SRAM 32Kx32 SYNC 3.3V PIPELINED BURST SRAM
Lifecycle:
New from this manufacturer.
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