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71V432S5PFG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
6.42
7
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Operation
(2)
OE ZZ I/O Status Power
Read L L Data Out (I/O
0
- I/O
31
)Active
Read H L High-Z Active
Write X L High-Z — Data In (I/O
0
- I/O
31
)Active
Deselected X L High-Z Standby
Sleep X H High-Z Sleep
3104 tbl 09
Operation GW BWE BW
1
BW
2
BW
3
BW
4
Read HHXXXX
Read HLHHHH
Write all Bytes LXXXXX
Write all Bytes HLLLLL
Write Byte 1
(2)
HLLHHH
Write Byte 2
(2)
HLHLHH
Write Byte 3
(2)
HLHHLH
Write Byte 4
(2)
HLHHHL
3104 tbl 08
Linear Burst Sequence Table (LBO=VSS)
Interleaved Burst Sequence Table (LBO=V
DD)
Asynchronous Truth Table
(1)
Synchronous Write Function Truth Table
(1)
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
NOTES:
1. L = V
IL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 0 0 1 1 1 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1)
11 10 01 00
3104 tbl 10
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 1 0 1 1 0 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1)
11 00 01 10
3104 tbl 11
6.42
8
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
+1.5V
50Ω
I/O
Z
0
=50Ω
3104 drw 03
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range
(1)
(VDD = 3.3V +10/-5%, VHD = VDD–0.2V, VLD = 0.2V)
Figure 3. Lumped Capacitive Load, Typical Derating
* Including scope and jig capacitance.
Figure 2. AC Test Load
(for tOHZ, tCHZ, tOLZ, and tDC1)
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range
(VDD = 3.3V +10/-5%, Commercial and Industrial Temperature Ranges)
AC Test Loads
1
2
3
4
20 30 50 100 200
Δt
CD
(Typical, ns)
Capacitance (pF)
80
5
6
3104 drw 05
351Ω
+3.3V
317Ω
5pF*
I/O
3104 drw 04
NOTE:
1. The LBO pin will be internally pulled to V
DD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
Symbol Parameter Test Conditions Min. Max.
Unit
|I
LI
| Input Leakage Current V
DD
= Max., V
IN
=
0V to V
DD
—5µA
|I
LI
| ZZ and LBO Input Leakage Current
(1 )
V
DD
= Max., V
IN
=
0V to V
DD
—30µA
|I
LO|
Output Leakage Current
CE >
V
IH
or OE > V
IH
, V
OUT
= 0V to V
DD
, V
DD
= Max.
—5µA
V
OL
Output Low Voltage (I/O
1
–I/O
31
)I
OL
= 5mA, V
DD
= Min. — 0.4 V
V
OH
Output High Voltage (I/O
1
–I/O
31
)I
OH
= –5mA, V
DD
= Min. 2.4 — V
3104 tbl 12
Figure 1. AC Test Load
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
0 to 3.0V
2ns
1.5V
1.5V
See Figures 1 and 2
3104 tbl 14
IDT71V432S5 IDT71V432S6
Symbol Parameter Test Conditions Com'l. Ind. Com'l. Ind.
Unit
I
DD
Operating Power Supply Current Device Selected, Outputs Open, V
DD
= Max.,
V
IN
> V
IH
or < V
IL
, f = f
MAX
(2)
200 200 180 180 mA
I
SB
Standby Power Supply Current Device Deselected, Outputs Open, V
DD
= Max.,
V
IN
> V
IH
or < V
IL
, f = f
MAX
(2)
65 65 60 60 mA
I
SB1
Full Standby Power Supply Current Device Deselected, Outputs Open, V
DD
= Max.,
V
IN
> V
HD
or < V
LD
, f = 0
(2)
15 15 15 15 mA
I
ZZ
Full Sleep Mode Power Supply Current ZZ > V
HD
, V
DD
= Max. 10 10 10 10 mA
3104 tbl 13a
6.42
9
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
NOTES:
1. Measured as HIGH above 2.0V and LOW below 0.8V.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
AC Electrical Characteristics
(VDD = 3.3V +10/-5%, Commercial and Industrial Temperature Ranges)
Symbol Parameter
71V432S5 71V432S6
Unit
Min. Max. Min. Max.
CLOCK PARAMETERS
t
CYC
Clock Cycle Time 10
____
12
____
ns
t
CH
(1)
Clock High Pulse Width 4
____
4.5
____
ns
t
CL
(1)
Clock Low Pulse Width 4
____
4.5
____
ns
OUTPUT PARAMETERS
t
CD
Clock High to Valid Data
____
5
____
6ns
t
CDC
Clock High to Data Change 1.5
____
2
____
ns
t
CLZ
(2)
Clock High to Output Active 0
____
0
____
ns
t
CHZ
(2)
Clock High to Data High-Z 1.5 5 2 5 ns
t
OE
Output Enable Access Time
____
5
____
5ns
t
OLZ
(2)
Output Enable Low to Data Active 0
____
0
____
ns
t
OHZ
(2)
Output Enable High to Data High-Z
____
4
____
5ns
SETUP TIMES
t
SA
Address Setup Time 2.5
____
2.5
____
ns
t
SS
Address Status Setup Time 2.5
____
2.5
____
ns
t
SD
Data in Setup Time 2.5
____
2.5
____
ns
t
SW
Write Setup Time 2.5
____
2.5
____
ns
t
SAV
Address Advance Setup Time 2.5
____
2.5
____
ns
t
SC
Chip Enable/Select Setup Time 2.5
____
2.5
____
ns
HOLD TIMES
t
HA
Address Hold Time 0.5
____
0.5
____
ns
t
HS
Address Status Hold Time 0.5
____
0.5
____
ns
t
HD
Data In Hold Time 0.5
____
0.5
____
ns
t
HW
Write Hold Time 0.5
____
0.5
____
ns
t
HAV
Address Advance Hold Time 0.5
____
0.5
____
ns
t
HC
Chip Enable/Select Hold Time 0.5
____
0.5
____
ns
SLEEP MODE AND CONFIGURATION PARAMETERS
t
ZZPW
ZZ Pulse Width 100 — 100
____
ns
t
ZZR
(3)
ZZ Recovery Time 100 — 100
____
ns
t
CFG
(4)
Configuration Set-up Time 40 — 50
____
ns
3104 tbl 15a
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

71V432S5PFG

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Buy 71V432S5PFG
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Description:
SRAM 32Kx32 SYNC 3.3V PIPELINED BURST SRAM
Lifecycle:
New from this manufacturer.
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