AD7793BRUZ-REEL Datasheet AD7793BRUZ-REEL, AD7793BRUZ, AD7792BRUZ-REEL | P16-P18

AD7792/AD7793

Rev. B | Page 16 of 32

Table 15. Operating Modes

MD2 MD1 MD0 Mode

0 0 0

Continuous Conversion Mode (Default).

In continuous conversion mode, the ADC continuously performs conversions and places the result in the data

RDY goes low when a conversion is complete. The user can read these conversions by placing the device in

continuous read mode, whereby the conversions are automatically placed on the DOUT line when SCLK pulses are

applied. Alternatively, the user can instruct the ADC to output the conversion by writing to the communications

is available after a period of 2/f

ADC

. Subsequent conversions are available at a frequency of f

ADC

0 0 1

Single Conversion Mode.

When single conversion mode is selected, the ADC powers up and performs a single conversion. The oscillator

requires 1 ms to power up and settle. The ADC then performs the conversion, which takes a time of 2/f

ADC

. The

conversion result is placed in the data register,

RDY goes low, and the ADC returns to power-down mode. The

conversion remains in the data register, and

RDY remains active low until the data is read or another conversion is

performed.

0 1 0

Idle Mode.

In idle mode, the ADC filter and modulator are held in a reset state, although the modulator clocks are still provided.

0 1 1

Power-Down Mode.

In power-down mode, all the AD7792/AD7793 circuitry is powered down, including the current sources, burnout

currents, bias voltage generator, and CLKOUT circuitry.

1 0 0

Internal Zero-Scale Calibration.

An internal short is automatically connected to the enabled channel. A calibration takes 2 conversion cycles to

complete.

RDY goes high when the calibration is initiated and returns low when the calibration is complete. The

ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of

the selected channel.

1 0 1

Internal Full-Scale Calibration.

A full-scale input voltage is automatically connected to the selected analog input for this calibration.

When the gain equals 1, a calibration takes 2 conversion cycles to complete. For higher gains, 4 conversion cycles

are required to perform the full-scale calibration.

RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed

in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the

selected channel.

Internal full-scale calibrations cannot be performed when the gain equals 128. With this gain setting, a system full-

scale calibration can be performed.

A full-scale calibration is required each time the gain of a channel is changed to minimize the full-scale error.

1 1 0

System Zero-Scale Calibration.

User should connect the system zero-scale input to the channel input pins as selected by the CH2 to CH0 bits. A

system offset calibration takes 2 conversion cycles to complete.

RDY goes high when the calibration is initiated and

returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured

offset coefficient is placed in the offset register of the selected channel.

1 1 1

System Full-Scale Calibration.

User should connect the system full-scale input to the channel input pins as selected by the CH2 to CH0 bits.

A calibration takes 2 conversion cycles to complete.

RDY goes high when the calibration is initiated and returns low

when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale

coefficient is placed in the full-scale register of the selected channel.

A full-scale calibration is required each time the gain of a channel is changed.

Table 16. Update Rates Available

FS3 FS2 FS1 FS0 f

ADC

(Hz) t

SETTLE

(ms) Rejection @ 50 Hz/60 Hz (Internal Clock)

0 0 0 0 x x

0 0 0 1 470 4

0 0 1 0 242 8

0 0 1 1 123 16

0 1 0 0 62 32

0 1 0 1 50 40

0 1 1 0 39 48

0 1 1 1 33.2 60

1 0 0 0 19.6 101 90 dB (60 Hz only)

AD7792/AD7793

Rev. B | Page 17 of 32

FS3 FS2 FS1 FS0 f

ADC

(Hz) t

SETTLE

(ms) Rejection @ 50 Hz/60 Hz (Internal Clock)

1 0 0 1 16.7 120 80 dB (50 Hz only)

1 0 1 0 16.7 120 65 dB (50 Hz and 60 Hz)

1 0 1 1 12.5 160 66 dB (50 Hz and 60 Hz)

1 1 0 0 10 200 69 dB (50 Hz and 60 Hz)

1 1 0 1 8.33 240 70 dB (50 Hz and 60 Hz)

1 1 1 0 6.25 320 72 dB (50 Hz and 60 Hz)

1 1 1 1 4.17 480 74 dB (50 Hz and 60 Hz)

CONFIGURATION REGISTER

RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x0710

The configuration register is a 16-bit register from which data can be read or to which data can be written. This register is used to con-

figure the ADC for unipolar or bipolar mode, enable or disable the buffer, enable or disable the burnout currents, select the gain, and

select the analog input channel.

Tabl e 17 outlines the bit designations for the filter register. CON0 through CON15 indicate the bit

locations; CON denotes that the bits are in the configuration register. CON15 denotes the first bit of the data stream. The number in

parentheses indicates the power-on/reset default status of that bit.

CON15 CON14 CON13 CON12 CON11 CON10 CON9 CON8

VBIAS1(0) VBIAS0(0) BO(0)

B(0)

BOOST(0) G2(1) G1(1) G0(1)

CON7 CON6 CON5 CON4 CON3 CON2 CON1 CON0

REFSEL(0) 0(0) 0(0) BUF(1) 0(0) CH2(0) CH1(0) CH0(0)

Table 17. Configuration Register Bit Designations

Bit Location Bit Name Description

CON15 to

CON14

VBIAS1 to

VBIAS0

Bias Voltage Generator Enable. The negative terminal of the analog inputs can be biased up to AV

/2. These

bits are used in conjunction with the boost bit.

VBIAS1 VBIAS0 Bias Voltage

0 0 Bias voltage generator disabled

0 1

Bias voltage connected to AIN1(−)

1 0

Bias voltage connected to AIN2(−)

1 1 Reserved

CON13 BO

Burnout Current Enable Bit. When this bit is set to 1 by the user, the 100 nA current sources in the signal path

are enabled. When BO = 0, the burnout currents are disabled. The burnout currents can be enabled only

when the buffer or in-amp is active.

CON12

B Unipolar/Bipolar Bit. Set by user to enable unipolar coding; that is, zero differential input results in 0x000000

output, and a full-scale differential input results in 0xFFFFFF output. Cleared by the user to enable bipolar

coding. Negative full-scale differential input results in an output code of 0x000000, zero differential input

results in an output code of 0x800000, and a positive full-scale differential input results in an output code of

0xFFFFFF.

CON11 BOOST

This bit is used in conjunction with the VBIAS1 and VBIAS0 bits. When set, the current consumed by the bias

voltage generator is increased. This reduces its power-up time.

CON10 to

CON8

G2 to G0 Gain Select Bits.

Written by the user to select the ADC input range as follows:

G2 G1 G0 Gain ADC Input Range (2.5 V Reference)

0 0 0 1 (In-amp not used) 2.5 V

0 0 1 2 (In-amp not used) 1.25 V

0 1 0 4 625 mV

0 1 1 8 312.5 mV

1 0 0 16 156.2 mV

1 0 1 32 78.125 mV

1 1 0 64 39.06 mV

1 1 1 128 19.53 mV

AD7792/AD7793

Rev. B | Page 18 of 32

Bit Location Bit Name Description

CON7 REFSEL Reference Select Bit. The reference source for the ADC is selected using this bit.

REFSEL Reference Source

0 External Reference Applied between REFIN(+) and REFIN(–).

1 Internal Reference Selected.

CON6 to

CON5

0 These bits must be programmed with a Logic 0 for correct operation.

CON4 BUF

Configures the ADC for buffered or unbuffered mode of operation. If cleared, the ADC operates in unbuffered

mode, lowering the power consumption of the device. If set, the ADC operates in buffered mode, allowing the

user to place source impedances on the front end without contributing gain errors to the system. The buffer

can be disabled when the gain equals 1 or 2. For higher gains, the buffer is automatically enabled.

With the buffer disabled, the voltage on the analog input pins can be from 30 mV below GND to 30 mV above

. When the buffer is enabled, it requires some headroom, so the voltage on any input pin must be limited

to 100 mV within the power supply rails.

CON3 0 This bit must be programmed with a Logic 0 for correct operation.

CON2 to

CON0

CH2 to

CH0

Channel Select Bits. Written by the user to select the active analog input channel to the ADC.

CH2 CH1 CH0 Channel Calibration Pair

0 0 0 AIN1(+) – AIN1(–) 0

0 0 1 AIN2(+) – AIN2(–) 1

0 1 0 AIN3(+) – AIN3(–) 2

0 1 1 AIN1(–) – AIN1(–) 0

1 0 0 Reserved

1 0 1 Reserved

1 1 0 Temp Sensor Automatically selects gain = 1 and internal reference

1 1 1 AV

Monitor

Automatically selects gain = 1/6 and 1.17 V

reference

DATA REGISTER

RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x0000(00)

The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from

this register, the

RDY

bit/pin is set.

ID REGISTER

RS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0xXA (AD7792)/0xXB (AD7793)

The identification number for the AD7792/AD7793 is stored in the ID register. This is a read-only register.

IO REGISTER

RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00

The IO register is an 8-bit register from which data can be read or to which data can be written. This register is used to enable and select

the value of the excitation currents.

Tabl e 18 outlines the bit designations for the IO register. IO0 through IO7 indicate the bit locations;

IO denotes that the bits are in the IO register. IO7 denotes the first bit of the data stream. The number in parentheses indicates the power-

on/reset default status of that bit.

IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0

0(0) 0(0) 0(0) 0(0) IEXCDIR1(0) IEXCDIR0(0) IEXCEN1(0) IEXCEN0(0)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P32

AD7793BRUZ-REEL

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Analog to Digital Converters - ADC 3Ch Lo Noise Lo Pwr 24B w/ On-Chip Ref

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AD7793BRUZ-REEL

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