AD7792/AD7793
Rev. B | Page 5 of 32
Parameter AD7792B/AD7793B
1
Unit Test Conditions/Comments
SCLK, CLK, and DIN (Schmitt-
Triggered Input)
2
V
T
(+) 1.4/2 V min/V max DV
DD
= 5 V
V
T
(–) 0.8/1.7 V min/V max DV
DD
= 5 V
V
T
(+) − V
T
(−)
0.1/0.17 V min/V max DV
DD
= 5 V
V
T
(+) 0.9/2 V min/V max DV
DD
= 3 V
V
T
(–) 0.4/1.35 V min/V max DV
DD
= 3 V
V
T
(+) − V
T
(−)
0.06/0.13 V min/V max DV
DD
= 3 V
Input Currents
Input Capacitance
±10
10
μA max
pF typ
V
IN
= DV
DD
or GND
All digital inputs
LOGIC OUTPUTS (INCLUDING CLK)
V
OH
, Output High Voltage
2
DV
DD
− 0.6
V min DV
DD
= 3 V, I
SOURCE
= 100 μA
V
OL
, Output Low Voltage
2
0.4 V max DV
DD
= 3 V, I
SINK
= 100 μA
V
OH
, Output High Voltage
2
4 V min DV
DD
= 5 V, I
SOURCE
= 200 μA
V
OL
, Output Low Voltage
2
0.4 V max
DV
DD
= 5 V, I
SINK
= 1.6 mA (DOUT/RDY)/800 μA
(CLK)
Floating-State Leakage Current ±10 μA max
Floating-State Output Capacitance 10 pF typ
Data Output Coding Offset binary
SYSTEM CALIBRATION
2
Full-Scale Calibration Limit +1.05 × FS V max
Zero-Scale Calibration Limit
−1.05 × FS
V min
Input Span 0.8 × FS V min
2.1 × FS V max
POWER REQUIREMENTS
7
Power Supply Voltage
AV
DD
to GND
2.7/5.25 V min/max
DV
DD
to GND
2.7/5.25 V min/max
Power Supply Currents
I
DD
Current 140 μA max
110 μA typ @ AV
DD
= 3 V, 125 μA typ @ AV
DD
= 5 V,
unbuffered mode, external reference
185 μA max
130 μA typ @ AV
DD
= 3 V, 165 μA typ @ AV
DD
= 5 V,
buffered mode, gain = 1 or 2, external reference
400 μA max
300 μA typ @ AV
DD
= 3 V, 350 μA typ @ AV
DD
= 5 V,
gain = 4 to 128, external reference
500 μA max
400 μA typ @ AV
DD
= 3 V, 450 μA typ @ AV
DD
= 5 V,
gain = 4 to 128, internal reference
I
DD
(Power-Down Mode) 1 μA max
1
Temperature range is –40°C to +105°C. At the 19.6 Hz and 39.2 Hz update rates, the INL, power supply rejection (PSR), common-mode rejection (CMR), and normal
mode rejection (NMR) do not meet the data sheet specification if the voltage on the AIN(+) or AIN(−) pins exceed AV
DD
− 16 V typically. When this voltage is exceeded,
the INL, for example, is reduced to 18 ppm of FS typically while the PSR is reduced to 69 dB typically. Therefore, for guaranteed performance at these update rates, the
absolute voltage on the analog input pins needs to be below AV
DD
− 1.6 V.
2
Specification is not production tested, but is supported by characterization data at initial product release.
3
Following a calibration, this error is in the order of the noise for the programmed gain and update rate selected.
4
Recalibration at any temperature removes these errors.
5
Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (AV
DD
= 4 V, gain = 1, T
A
= 25°C).
6
FS[3:0] are the four bits used in the mode register to select the output word rate.
7
Digital inputs equal to DV
DD
or GND with excitation currents and bias voltage generator disabled.
