LT3507
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For more information www.linear.com/LT3507
and is largest when V
IN
=2V
OUT
(50% duty cycle). As
the second, lower power channel draws input current,
the input capacitors RMS current actually decreases as
the out-of-phase current cancels the current drawn by the
higher power channel. Considering that the maximum load
current from a single phase (if SW2 and SW3 are both at
maximum current) is ~3A, RMS ripple current will always
be less than 1.5A.
The high frequency of the LT3507 reduces the energy
storage requirements of the input capacitor, so that the
capacitance required is often less than 10µF. The combi
-
nation of small size and low impedance (low equivalent
series resistance or ESR) of ceramic capacitors makes
them the preferred choice. The low ESR results in ver
y
low
voltage ripple. Ceramic capacitors can handle larger
magnitudes of ripple current than other capacitor types
of the same value. Use X5R and X7R types.
An alternative to a high value ceramic capacitor is a lower
value along with a larger electrolytic capacitor, for example
a 1µF ceramic capacitor in parallel with a low ESR tantalum
capacitor. For the electrolytic capacitor, a value larger than
10µF will be required to meet the ESR and ripple current
requirements. Because the input capacitor is likely to see
high surge currents when the input source is applied, tan
-
talum capacitors should be surge rated. The manufacturer
may also recommend operation below the rated voltage
of the capacitor. Be sure to place the
1µF ceramic as close
as possible to the V
IN
and GND pins on the IC for optimal
noise immunity.
A final caution is in order regarding the use of ceramic
capacitors at the input. A ceramic input capacitor can
combine with stray inductance to form a resonant tank
circuit. If power is applied quickly (for example by plugging
the circuit into a live power source), this tank can ring,
doubling the input voltage and damaging the LT3507. The
solution is to either clamp the input voltage or dampen the
tank circuit by adding a lossy capacitor in parallel with the
ceramic capacitor. For details, see Application Note 88.
Frequency Compensation
The LT3507 uses current mode control to regulate the
output. This simplifies loop compensation. In particular, the
LT3507 does not depend on the ESR of the output capacitor
for stability so you are free to use ceramic capacitors to
achieve low output ripple and small circuit size.
The components tied to the V
C
pin provide frequency
compensation. Generally, a capacitor and a resistor in
series to ground determine loop gain. In addition, there
is a lower value capacitor in parallel. This capacitor filters
noise at the switching frequency and is not part of the
loop compensation.
Loop compensation determines the stability and transient
performance. Designing the compensation network is a bit
complicated and the best values depend on the application
and the type of output capacitor. A practical approach is to
start with one of the circuits in this data sheet that is similar
to your application and tune the compensation network
to optimize the performance. Check stability across all
operating conditions, including load current, input voltage
and temperature. The LT1375 data sheet contains a more
thorough discussion of loop compensation and describes
how to test the stability using a transient load. Application
Note 76 is an excellent source as well.
Figure 6 shows an equivalent circuit for the LT3507 control
loop. The error amp is a transconductance amplifier with
finite output impedance. The power section, consisting of
the modulator, power switch and inductor is modeled as a
transconductance amplifier generating an output current
proportional to the voltage at the V
C
pin. The gain of the
power stage (g
mp
) is 5S for Channel 1 and 3.6S for Chan-
nels 2 and 3. Note that the output capacitor integrates this
applications inForMation
LT3507
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current and that the capacitor on the V
C
pin (C
C
) integrates
the error amplifier output current, resulting in two poles
in the loop. In most cases, a zero is required and comes
either from the output capacitor ESR or from a resistor
in series with C
C
. This model works well as long as the
inductor current ripple is not too low (ΔI
RIPPLE
> 5% I
OUT
)
and the loop crossover frequency is less than f
SW
/5. A
phase lead capacitor (C
PL
) across the feedback divider
may improve the transient response.
SHUTDOWN
The RUN pins are used to place the individual switching
regulators and the internal bias circuits in shutdown mode.
When all three RUN pins are pulled low, the LT3507 is in
shutdown mode and draws less than 1µA from the input
supply. When any RUN pin is pulled high (>1.25V) the
internal reference, the LDO and selected channel are all
turned on.
The RUN pins draw a small amount of current to power
the reference. The current is less than 3µA at 1.8V, so the
RUN pin can be driven directly from 1.8V logic. The RUN
pins are rated up to 36V and can be connected directly to
the input voltage.
A RUN pin cannot be pulled up by logic powered by its
own output, i.e., RUN1 cant be pulled up by logic powered
by OUT1.
POWER GOOD INDICATORS
The PGOOD pin is the open-collector output of an internal
comparator. PGOOD remains low until the FB pin is within
10% of the final regulation voltage. Tie the PGOOD to any
supply with a pull-up resistor that will supply less than
200µA. Note that this pin will be open when the LT3507
is in shutdown mode (all three RUN pins at ground) re
-
gardless of the voltage at the FB pin. PGOOD is valid when
the LT3507 is enabled (any RUN pin is high) and V
IN
is
greater than ~3.5V.
OUTPUT SEQUENCING
The LT3507 outputs can be sequenced in several ways.
The circuits in Figure 7 show some examples of these. In
each case channel 1 starts first, followed by channel 2,
then channel 3. The sequence shown is not a requirement;
the LT3507 can sequence the channels in any order. Note
that these circuits sequence the outputs during start-up.
When shut down the three channels turn off simultaneously.
applications inForMation
Figure 6. Loop Response Model
+
V
FB
800mV
V
SW
V
C
LT3507
GND
3507 F06
R1
OUTPUT
ESR
C
F
C
C
R
C
500k
ERROR
AMPLIFIER
FB
R2
C1
C1
CURRENT MODE
POWER STAGE
g
mp
330µS
+
POLYMER
OR
TANTALUM
CERAMIC
C
PL
LT3507
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For more information www.linear.com/LT3507
The most obvious method is to bring the RUN pins up
individually in the sequence desired (Figure 7a). This is
the ideal solution if full independent control of all three
channels is needed. This is also a simple solution, but it
does require three logic inputs.
Another possibility is to use the soft-start feature to slow
the start-up of specific channels (Figure 7b). All three RUN
pins are tied together and the difference in soft-start ca
-
pacitance will determine the start-up sequence. The larger
capacitor on channel 2 slows its start-up with respect to
channel 1, and channel 3 is even slower
. The capacitor on
the delayed channel should be at least twice the value of
the capacitor on the faster channel. A larger ratio may be
r
equired, depending on the output capacitance and load on
each channel. Make sure to test the circuit in the system
before deciding on final values for these capacitors. Also
remember that the delayed channels will start rising right
away, just at a slower rate than the faster channels.
The PG pins can be also used to sequence the three out
-
puts. In Figure 7c, the PG pins drive the RUN pins directly.
Channel 2 will be held off until channel 1 is in regulation
and channel 3 is held off until channel 2 is in regulation.
The
resistors
pull up to V
INSW
so that there is no current
draw in shutdown. They should be sized to provide at least
1µA into the RUN pin. The capacitors keep channels 2 and 3
off until the power good comparators are functioning (the
power good comparators are disabled in shutdown). The
FETs are necessary to insure the RUN2 and RUN3 pins
are held low during shutdown.
In Figure 7d, the PG pins pull down the TRK/SS pins of
the delayed channels. This is a simple solution requiring
no extra components. Channel 2 is held off by the PG1
output pulling TRK/SS2 down until channel 1 is at 90% of
its final value. PG1 then goes high impedance and allows
the channel 2 soft-start circuit to charge the soft-start
capacitor bringing channel 2 up. Similarly, channel 3 is
held off by PG2.
The circuits in Figure 7a and 7b leave the power good
indicators free. However, the circuits in Figures 7c and
7d have another advantage. As well as sequencing the
outputs at start-up, they also disable the slaved channels
if the master channel falls out of regulation (due to a short
circuit or a collapsing input voltage).
Finally, be aware that the circuit in Figure 7e does not
work, because the power good comparators are disabled
in shutdown.
applications inForMation
Figure 7. Output Sequencing
RUN1
RUN2
RUN3
TRK/SS1
TRK/SS2
TRK/SS3
LT3507
C
2C
4C
(7b)
RUN1
RUN2
RUN3
RUN1
RUN2
RUN3
LT3507
(7a)
RUN2
PG1
LT3507
V
IN
(7e)
Doesn’t Work!
RUN1RUNRUN
V
INSW
PG1
RUN2
RUN3
PG2
3507 F07
LT3507
(7c)
RUN1
RUN2
RUN3
TRK/SS1
PG1
TRK/SS2
PG2
TRK/SS3
LT3507
(7d)
RUN

LT3507EUHF#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 3x Mono Buck Reg w/ LDO
Lifecycle:
New from this manufacturer.
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