LT3507
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3507fb
For more information www.linear.com/LT3507
pin Functions
BOOST1, BOOST2, BOOST3 (Pins 1, 27, 32): The BOOST
pins are used to provide drive voltages, higher than the
input voltage, to the internal bipolar NPN power switches.
These pins must be tied through a diode from V
OUT
, V
IN
or another supply greater than 2.5V.
V
IN1
(Pins 2, 3): The V
IN1
pins supply power to the internal
switch of the 2.4A regulator and to the LT3507’s internal
reference and start-up circuitry. V
IN1
must be above the
internal UVLO threshold of 3.8V (typical) for any of the
four channels to operate. These pins must be locally
bypassed (Note 6).
V
INSW
(Pin 4): The V
INSW
pin is a switched V
IN1
for the
user programmable undervoltage and overvoltage detec-
tion. It is connected to V
IN1
when any of the RUN pins
are pulled high, and high impedance when all RUN pins
are low or open.
OVLO (Pin 5): The LT3507 goes into overvoltage shutdown
when this pin goes above 1.2V. If unused, the OVLO pin
should be tied to GND.
UVLO (Pin 6): The LT3507 goes into undervoltage shut
-
down when this pin drops below 1.2V. If unused, the UVLO
pin should be tied to V
INSW
.
V
C1
, V
C2
, V
C3
(Pins 7, 23, 19): The V
C
pins are the outputs
of the internal error amps. The voltages on these pins
control the peak switch currents. These pins are normally
used to compensate the control loops. Each switching
regulator can be shut down by pulling its respective V
C
pin to ground with an NMOS or NPN transistor.
TRK/SS1, TRK/SS2, TRK/SS3, TRK/SS4 (Pins 8, 21, 18,
26): The TRK/SS pins allow a regulator to track the output
of another regulator. When the TRK/SS pin is below 0.8V,
the FB pin regulates to the TRK/SS voltage. This pin can
also be used as a soft-start by connecting a capacitor from
TRK/SS to ground. The TRK/SS pins should be left open
if neither feature is used.
FB1, FB2, FB3 (Pins 9, 22, 20): The FB pins are the nega
-
tive inputs of the error amplifiers. The LT3507 regulates
each feedback pin to the lesser of
0.8V or the TRK/SS
pin voltage. Connect the feedback resistor divider taps
to these pins.
Note 6: V
INX
pins that are connected together may share a bypass capacitor.
PGOOD1, PGOOD2, PGOOD3 (Pins 10, 11, 12): The
PGOOD pins are the open-collector outputs of an internal
comparator. PGOOD remains low until the FB pin is within
10% of the final regulation voltage. As well as indicating
output regulation, the PGOOD pins can sequence the
switching regulators. These pins must be left unconnected
if unused. The PGOOD outputs are valid when V
IN
is greater
than 3.8V and any of the RUN pins are high. They are not
valid when all RUN pins are low.
R
T
/SYNC (Pin 13): The R
T
/SYNC pin requires a resistor
to ground or a clock signal to set the operating frequency
of the LT3507.
RUN1, RUN2, RUN3 (Pins 14, 15, 16): The RUN pins are
used to shut down the individual switching regulators.
When all three RUN pins are low, the LT3507 shuts down
and draws less than 1µA from V
IN1
.
BIAS (Pin 17): The BIAS pin supplies the current to the
LT3507’s internal regulator. This pin should be tied to the
lowest available voltage source above 3V (either V
IN
, V
OUT
or any other available supply). The LDO pass transistor’s
base current is supplied from the BIAS pin if it is at least
0.8V above the LDO DRIVE output.
DRIVE (Pin 24): The DRIVE pin provides the base drive
for an external NPN transistor used for the LDO regulator.
FB4 (Pin 25): The FB4 pin is the negative input to the LDO
error amplifier. It is regulated to 0.8V through the LDO
feedback resistor divider.
V
IN2
(Pins 30, 31)/V
IN3
(Pins 35, 36 ): The V
IN2
and V
IN3
pins supply power to the internal switches of the 1.5A
converters. These pins must be locally bypassed (Note 6).
SW1 (Pins 37, 38)/SW2 (Pins 28, 29)/SW3 (Pins 33, 34):
The SW pins are the outputs of the internal power switches.
Connect these pins to the inductors and switching diodes.
Exposed Pad (Pin 39): Ground. The underside Exposed
Pad metal of the package provides both electrical contact
to ground and good thermal contact to the printed circuit
board. The Exposed Pad must be soldered to a grounded
pad on the circuit board for proper operation.
LT3507
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3507fb
For more information www.linear.com/LT3507
block DiaGraM
Figure 1. LT3507 Block Diagram with Typical External Components
+
+
+
+
+
+
+
+
+
+
1.2V
OVLO
V
INSW
UVLO
DRIVE
V
IN4
V
OUT4
0.8V
TRK/SS4
FB4
BOOST
SW
FB
TRK/SS
3507 F01
V
IN
SHDN
V
INX
C
IN
C3
V
OUTX
C1
D2
D1
0.8V
80mV
ONE OF THREE STEP-DOWN REGULATORS
ERROR
AMP
I
LIMIT
CLAMP
1.25µA
L1
R1
R2
UNDERVOLTAGE
DETECTION
THERMAL
SHUTDOWN
CHANNEL
SHUTDOWN
0.9V
C1
0.4V
V
C
R
C
C
C
C
F
PGOOD
1.7V
SLOPE
CLK
S Q
R
+
SLAVE
OSC
+
+
RUN1
BIAS
V
IN1
RUN2
RUN3
R
T
/SYNC
GND
MASTER
OSC
INT REG
AND REF
CLK1
CLK2
CLK3
LT3507
9
3507fb
For more information www.linear.com/LT3507
operation
The LT3507 contains three independent, constant fre-
quency, current mode, switching regulators with internal
power switches plus a low dropout linear regulator. The
three regulators share common cir
cuitry including input
source, voltage reference and oscillator, but are otherwise
independent. Operation can be best understood by refer
-
ring to the Block Diagram (Figure 1).
If the RUN pins are tied to ground, the
LT3507
is shut
down and draws <1µA from the input source tied to V
IN1
. If
any of the RUN pins are driven above 1V, the internal bias
circuits turn on, including the internal regulator, reference,
and master oscillator. Each switching regulator will only
begin to operate when its corresponding RUN pin reaches
>1.25V. The master oscillator generates three clock signals,
with the signal for Channel 1 out of phase by 180°.
The three switchers are current mode regulators. Instead
of directly modulating the duty cycle of the power switch,
the feedback loop controls the peak current in the switch
during each cycle. Compared to voltage mode control, cur
-
rent mode control improves loop dynamics and provides
cycle-by-cycle current limit.
The Block Diagram shows only one of the three step-down
switching regulators. A pulse from the slave oscillator
sets
the
RS flip-flop and turns on the internal NPN bipo
-
lar power switch. Current in the switch and the external
inductor begins to increase. When this current exceeds a
level determined by the voltage at V
C
, current comparator
C1 resets the flip-flop, turning off the switch. The current
in the inductor flows through the external Schottky diode
and begins to decrease. The cycle begins again at the next
pulse from the oscillator. In this way, the voltage on the V
C
pin controls the current through the inductor to the output.
The internal error amplifier regulates the output voltage
by continually adjusting the V
C
pin voltage. The threshold
for switching on the V
C
pin is >0.9V and an active clamp
of 1.8V limits the output current.
Each switcher contains an extra, independent oscillator to
perform frequency foldback during overload conditions.
This slave oscillator is normally synchronized to the master
oscillator. A comparator senses when V
FB
is less than 50%
of its regulated value and switches the regulator from the
master oscillator to a slower slave oscillator. V
FB
is less than
50% of its regulated value during start-up, short-circuit
and overload conditions. Frequency foldback helps limit
switch current under these conditions.
The TRK/SS pins override the 0.8V reference for the FB
pins when the TRK/SS pins are below 0.8V. This allows
either coincident or ratiometric supply tracking on start-up
as well as a soft-start capability.
The switch drivers operate either from V
IN
or from the
BOOST pin. An external capacitor and diode are used to
generate a voltage at the BOOST pin that is higher than
the input supply. This allows the driver to saturate the
internal bipolar NPN power switch for efficient operation.
The BIAS pin allows the internal circuitry to draw its current
from a lower voltage supply than the input, also reducing
power dissipation and increasing efficiency. If the voltage
on the BIAS pin falls below 3V, then its quiescent current
will flow from V
IN
.
A power good comparator trips when the FB pin is at
90% of its regulated value. The PGOOD output is an
open-collector transistor that is off when the output is in
regulation, allowing an external resistor to pull the PGOOD
pin high. Power good is valid when the LT3507 is enabled
and V
IN
> 3.5V.
The LDO regulator uses an external NPN pass transistor to
form a linear regulator. The loop is internally compensated
to be stable with a load capacitance of 2.2µF or greater.
The LDO is disabled when all three of the RUN pins are low.
The overvoltage and undervoltage detection shuts down
the LT3507 if the OVLO pin>1.2V or the UVLO pin<1.2V.
Input overvoltage and undervoltage values are set by re
-
sistor dividers to V
INSW
. Hysteresis is provided by 10µA
currents activated when either pin trips. The hysteresis
voltage at V
IN
is the top resistor times 10µA.

LT3507EUHF#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 3x Mono Buck Reg w/ LDO
Lifecycle:
New from this manufacturer.
Delivery:
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