13
Integrated
Circuit
Systems, Inc.
ICS9EPRS475
Datasheet
1615—08/19/09
SMBUS Table: SRC Frequency Control Register
Byte 25 Name Control Function Type 0 1 Default
Bit 7
N Div2 N Divider Prog bit 2 RW X
Bit 6
N Div1 N Divider Prog bit 1 RW X
Bit 5
M Div5 RW X
Bit 4
M Div4 RW X
Bit 3
M Div3 RW X
Bit 2
M Div2 RW X
Bit 1
M Div1 RW X
Bit 0
M Div0 RW X
SMBUS Table: SRC Frequency Control Register
Byte 26 Name Control Function Type 0 1 Default
Bit 7
N Div10 RW X
Bit 6
N Div9 RW X
Bit 5
N Div8 RW X
Bit 4
N Div7 RW X
Bit 3
N Div6 RW X
Bit 2
N Div5 RW X
Bit 1
N Div4 RW X
Bit 0
N Div3 RW X
SMBUS Table: CPU Output Divider Control Register
Byte 27 Name Control Function Type 0 1 Default
Bit 7
HTTDiv3 RW 0000:/2 ; 0100:/4 1000:/8 ; 1100:/16 X
Bit 6
HTTDiv2 RW N/A ; 0101:/6 1001:/12 ; 1101:/24 X
Bit 5
HTTDiv1 RW N/A ; 0110:/10 1010:/20 ; 1110:/40 X
Bit 4
HTTDiv0 RW N/A ; 0111:/18 1011:/36 ; 1111:/72 X
Bit 3
CPUDiv3 RW 0000:/2 ; 0100:/4 1000:/8 ; 1100:/16 X
Bit 2
CPUDiv2 RW 0001:/3 ; 0101:/6 1001:/12 ; 1101:/24 X
Bit 1
CPUDiv1 RW 0010:/5 ; 0110:/10 1010:/20 ; 1110:/40 X
Bit 0
CPUDiv0 RW 0011:/9 ; 0111:/18 1011:/36 ; 1111:/72 X
SMBUS Table: CPU PLL Spread Spectrum Control Register
Byte 28 Name Control Function Type 0 1 Default
Bit 7
SSP7 RW X
Bit 6
SSP6 RW X
Bit 5
SSP5 RW X
Bit 4
SSP4 RW X
Bit 3
SSP3 RW X
Bit 2
SSP2 RW X
Bit 1
SSP1 RW X
Bit 0
SSP0 RW X
SMBUS Table: CPU PLL Spread Spectrum Control Register
Byte 29 Name Control Function Type 0 1 Default
Bit 7
SSP15 RW X
Bit 6
SSP14 RW X
Bit 5
SSP13 RW X
Bit 4
SSP12 RW X
Bit 3
SSP11 RW X
Bit 2
SSP10 RW X
Bit 1
SSP9 RW X
Bit 0
SSP8 RW X
Spread Spectrum Programming
b(15:8)
These bits set the CPU/HTT spread
pecentage.Please contact ICS for the appropriate
values.
Spread Spectrum Programming b(7:0)
These bits set the CPU/HTT spread
pecentage.Please contact ICS for the appropriate
values.
N Divider Programming Byte16
bit(7:0) and Byte15 bit(7:6)
The decimal representation of M and N Divider in
Byte 20 and 21 configure the SRC VCO
frequency. See M/N Caculation Tables for VCO
frequency formulas.
NOTE: Changing this frequency will also alter the
ATIG and SB_SRC frequencies by a similar
amount.
HTT Divider Ratio Programming Bits
CPU Divider Ratio Programming Bits
The decimal representation of M and N Divider in
Byte 20 and 21 configure the SRC VCO
frequency. See M/N Caculation Tables for VCO
frequency formulas.
NOTE: Changing this frequency will also alter the
ATIG and SB_SRC frequencies by a similar
amount.
M Divider Programming
bit (5:0)
