Not recommended for new designs. IRS20954SPBF
Please use IRS20957SPBF.
www.irf.com 21
Figure 21: Negative V
SS
Clamping
Junction Temperature Estimation
The power dissipation in the IRS20954 consists of following dominant items;
- P
MID
: dissipation in floating input logic and protection
- P
LOW
: dissipation in low-side
- P
HIGH
: dissipation in high-side
1. P
MID
: Dissipation in Floating Input Section
The dissipation in floating input section is given by;
DD
DD
DDBUS
LDDZDDMID
V
R
VV
PPP
⋅
−
≈
+=
+
Where
P
ZDD
is dissipation from internal zener diode clamping V
DD
voltage.
P
LDD
is dissipation from internal logic circuitry.
V
+BUS
is positive bus voltage feeding V
DD
from.
R
DD
is a resistor feeding V
DD
from V
+BUS
.
For obtaining a value of R
DD
, refer to Supplying V
DD
section above.
2. P
LOW
: Dissipation in Low-side
The dissipation in low-side includes loss from logic circuitry and loss from driving LO, and is given by;
()
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
++
⋅⋅⋅+⋅=
+=
(int)ggO
O
SWgCCQCC
LOLDDLOW
RRR
R
fQVccVI
PPP
Where
P
LDD
is dissipation from internal logic circuitry.
P
LO
is dissipation from gate drive stage to LO.
R
O
is equivalent output impedance of LO, typically 10 Ω for the IRS20954.
R
g(int)
is internal gate resistance of MOSFET.
R
g
is external gate resistance.
Qg is total gate charge of low-side MOSFET.
3. P
HIGH
: Dissipation in High-side
The dissipation in high-side includes loss from logic circuitry and loss from driving LO and is given by;