NCP4208MNR2G Datasheet NCP4208MNR2G | P10-P12

NCP4208

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Theory of Operation

The NCP4208 is an 8−phase VR11 controller; it combines

a multi−mode, fixed frequency PWM control with

multi−phase logic outputs for use in multi−phase

synchronous buck CPU core supply power converters. In

addition, the NCP4208 incorporates a serial interface to

allow the programming of key system performance

specifications and read back CPU data such as voltage,

current and power. Multiphase operation is important for

producing the high currents and low voltages demanded by

today’s microprocessors. Handling the high currents in a

single−phase converter would place high thermal demands

on the components in the system such as the inductors and

MOSFETs.

Startup Sequence

The NCP4208 follows the VR11 startup sequence shown

in Figure 7. After both the EN and UVLO conditions are

met, a programmable internal timer goes through one cycle

TD1. This delay cycle is programmed using Delay

Command, default delay = 2 ms). The first eight clock

cycles of TD2 are blanked from the PWM outputs and used

for phase detection as explained in the following section.

Then the programmable internal soft−start ramp is enabled

(TD2) and the output comes up to the boot voltage of 1.1 V.

The boot hold time is also set by the Delay Command. This

second delay cycle is called TD3. During TD3 the processor

VID pins settle to the required VID code. When TD3 is over,

the NCP4208 reads the VID inputs and soft starts either up

or down to the final VID voltage (TD4). After TD4 has been

completed and the PWRGD masking time (equal to VID

OTF masking) is finished, a third cycle of the internal timer

sets the PWRGD blanking (TD5).

The internal delay and soft−start times are programmable

using the serial interface and the Delay Command and

Soft−Start Command.

Figure 7. System Startup Sequence for VR11

TD1

5.0 V

SUPPLY

VTT I/O

(NCP4208 EN)

VCC_CORE

VR READY

(ADP4000 PWRGD)

CPU

VID INPUTS

BOOT

VID

UVLO

THRESHOLD

0.85 V

TD5

(1.1 V)

VID INVALID

TD4

TD2

TD3

VID VALID

50 m

Soft−Start

The Soft−Start slope for the output voltage is set by an

internal timer. The default value is 0.5 V/msec, which can be

programmed through the I

C interface. After TD1 and the

phase detection cycle have been completed, the SS time

(TD2 in Figure 7) starts. The SS circuit uses the internal VID

DAC to increase the output voltage in 6.25 mV steps up to

the 1.1 V boot voltage.

Once the SS circuit has reached the boot voltage, the boot

voltage delay time (TD3) is started. The end of the boot

voltage delay time signals the beginning of the second

soft−start time (TD4). The SS voltage changes from the boot

voltage to the programmed VID DAC voltage (either higher

or lower) using 6.25 mV steps.

The soft− start slew rate is programmed using Bits <2:0>

of the Ton_Rise (0xD5) command code. Table 1. Soft−Start

Codes provides the soft−start values. Figure 8 shows typical

startup waveforms for the NCP4208.

Table 1. Soft−Start Codes

Code Soft−Start (V/msec)

000 0.3

001 0.3

010 0.5 = default

011 0.7

100 0.9

101 1.1

110 1.3

111 1.5

Figure 8. Typical Startup Waveforms

Channel 1: CSREF, Channel 2: EN, Channel 3: PWM1

Phase Detection

During startup, the number of operational phases and their

phase relationship is determined by the internal circuitry that

monitors the PWM outputs. Normally, the NCP4208 operates

as an 8−phase PWM controller.

To operate as a 7−phase controller connect PWM8 to V

To operate as a 6−phase controller, connect PWM7 and

PWM8 to V

. To operate as a 5−phase controller connect

PWM6, PWM7 and PWM8 to V

. To operate as a 4−phase

controller, connect PWM5, PWM6, PWM7 and PWM8 to

. To operate as a 3−phase controller, connect PWM4,

PWM5, PWM6, PWM7 and PWM8 to V

. To operate as

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a 2−phase controller connect PWM3, PWM4, PWM5,

PWM6, PWM7 and PWM8 to V

. To operate as a 1−phase

controller connect PWM2, PWM3, PWM4, PWM5,

PWM6, PWM7 and PWM8 to V

Prior to soft−start, while EN is low, the PWM8, PWM7,

PWM6, PWM5, PWM4, PWM3 and PWM2 pins sink

approximately 100 mA each. An internal comparator checks

each pin’s voltage vs. a threshold of 3.0 V. If the pin is tied

to V

, it is above the threshold. Otherwise, an internal

current sink pulls the pin to GND, which is below the

threshold. PWM1 is low during the phase detection interval

that occurs during the first eight clock cycles of TD2. After

this time, if the remaining PWM outputs are not pulled to

, the 100 mA current sink is removed, and they function

as normal PWM outputs. If they are pulled to V

, the

100 mA current source is removed, and the outputs are put

into a high impedance state.

The PWM outputs are logic−level devices intended for

driving fast response external gate drivers such as the

ADP3121. Because each phase is monitored independently,

operation approaching 100% duty cycle is possible. In

addition, more than one output can be on at the same time to

allow overlapping phases.

Master Clock Frequency

The clock frequency of the NCP4208 is set with an

external resistor connected from the RT pin to ground. The

frequency follows the graph in Figure 3. To determine the

frequency per phase, the clock is divided by the number of

phases in use. If all phases are in use, divide by 8. If 4 phases

are in use divide by 4.

Output Voltage Differential Sensing

The NCP4208 combines differential sensing with a high

accuracy VID DAC and reference, and a low offset error

amplifier. This maintains a worst−case specification of

±9 mV differential sensing error over its full operating

output voltage and temperature range. The output voltage is

sensed between the FB pin and FBRTN pin. FB is connected

through a resistor, R

to the regulation point, usually the

remote sense pin of the microprocessor. FBRTN is

connected directly to the remote sense ground point. The

internal VID DAC and precision reference are referenced to

FBRTN, which has a minimal current of 70 mA to allow

accurate remote sensing. The internal error amplifier

compares the output of the DAC to the FB pin to regulate the

output voltage.

Output Current Sensing

The NCP4208 provides a dedicated current sense

amplifier (CSA) to monitor the total output current for

proper voltage positioning vs. load current, for the I

MON

output and for current limit detection. Sensing the load

current at the output gives the total real time current being

delivered to the load, which is an inherently more accurate

method than peak current detection or sampling the current

across a sense element such as the low−side MOSFET. This

amplifier can be configured several ways, depending on the

objectives of the system, as follows:

• Output inductor DCR sensing without a thermistor for

lowest cost.

• Output inductor DCR sensing with a thermistor for

improved accuracy with tracking of inductor

temperature.

• Sense resistors for highest accuracy measurements.

The positive input of the CSA is connected to the

CSREF pin, which is connected to the average output

voltage. The inputs to the amplifier are summed together

through resistors from the sensing element, such as the

switch node side of the output inductors, to the inverting

input CSSUM. The feedback resistor between CSCOMP

and CSSUM sets the gain of the amplifier and a filter

capacitor is placed in parallel with this resistor. The gain of

the amplifier is programmable by adjusting the feedback

resistor. This difference signal is used internally to offset the

VID DAC for voltage positioning. This different signal can

be adjusted between 50%−150% of the external value using

the I

C Loadline Calibration (0xDE) and Loadline Set

(0xDF) commands.

The difference between CSREF and CSCOMP is then

used as a differential input for the current limit comparator.

To provide the best accuracy for sensing current, the CSA

is designed to have a low offset input voltage. Also, the

sensing gain is determined by external resistors to make it

extremely accurate.

The CPU current can also be monitored over the I

interface. The current limit and the loadline can be

programmed over I

C interface.

Loadline Setting

The Loadline is programmable over the I

C on the

NCP4208. It is programmed using the Loadline Calibration

(0xDE) and Loadline Set (0xDF) commands. The Loadline

can be adjusted between 0% and 100% of the external R

CSA.

In this example R

CSA

= 1 mW. R

needs to be 0.8 mW,

therefore programming the Loadline Calibration + Loadline

Set register to give a combined percentage of 80% will set

the R

to 0.8 mW.

Table 2. Loadline Commands

Code Loadline (as a percentage of R

CSA

)

0 0000 0%

0 0001 3.226%

1 0000 51.6% = default

1 0001 53.3%

1 1110 96.7%

1 1111 100%

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Current Limit Setpoint

The current limit threshold on the NCP4208 is

programmed by a resistor between the I

ILIMFS

pin and the

CSCOMP pin. The I

ILIMFS

current, I

ILIMFS

, is compared

with an internal current reference of 20 mA. If I

ILIMFS

exceeds 20 mA then the output current has exceeded the limit

and the current limit protection is tripped.

ILIMFS

* V

CSCOMP

ILIMFS

(eq. 1)

Where V

ILIMFS

= V

CSREF

* V

CSCOMP

LOAD

(eq. 2)

ILIMFS

CSREF

* V

CSCOMP

ILIMFS

Where R

= DCR of the Inductor.

Assuming that:

+ 1mW

(eq. 3)

i.e. the external circuit is set up for a 1 mW Loadline then

the R

ILIMFS

is calculated as follows:

ILIMFS

1mW I

LOAD

ILIMIFS

(eq. 4)

Assuming we want a current limit of 150 A that means that

LIMFS

must equal 20 mA at that load.

20 mA +

1mW 150 AD

ILIMIFS

+ 7.5 kW

(eq. 5)

Solving this equation for R

LIMITFS

we get 7.5 kW.

The current limit threshold can be modified from the

resistor programmed value by using the I

C interface using

Bits <4:0> of the Current Limit Threshold command

(0xE2). The limit is programmable between 50% of the

external limit and 146.7% of the external limit. The

resolution is 3.3%. Table 3 gives some examples codes.

Table 3. Current Limit

Code Current Limit (% of External Limit)

0 0000 50%

0 0001 53.3%

1 0000 100% = default

1 0001 103.3%

1 1110 143.3%

1 1111 146.7%

Active Impedance Control Mode

For controlling the dynamic output voltage droop as a

function of output current, the CSA gain and loadline

programming can be scaled to be equal to the droop

impedance of the regulator times the output current. This

droop voltage is then used to set the input control voltage to

the system. The droop voltage is subtracted from the DAC

reference input voltage directly to tell the error amplifier

where the output voltage should be. This allows enhanced

feed−forward response.

Output Current Monitor

MON

is an analog output from the NCP4208 representing

the total current being delivered to the load. It outputs an

accurate current that is directly proportional to the current

set by the I

LIMFS

resistor. The current is then run through a

parallel RC connected from the I

MON

pin to the FBRTN pin

to generate an accurately scaled and filtered voltage as per

the VR11.1 specification. The size of the resistor is used to

set the I

MON

scaling.

(eq. 6)

IMON

+ 10

CSA

LOAD

ILIMFS

and

(eq. 7)

CSA

DCR

(

inductor

)

RCS

If the I

MON

and the OCP need to be changed based on the

TDC of the CPU, then the I

LIMFS

resistor is the only

component that needs to be changed. If the I

MON

scaling is

the only change needed then changing the I

MON

resistor

accomplishes this.

The I

MON

pin also includes an active clamp to limit the

MON

voltage to 1.15 V MAX while maintaining 900 mV

MIN full scale accurate reporting.

Current Control Mode and Thermal Balance

The NCP4208 has individual inputs (SW1 to SW8) for

each phase that are used for monitoring the current of each

phase. This information is combined with an internal ramp

to create a current balancing feedback system that has been

optimized for initial current balance accuracy and dynamic

thermal balancing during operation. This current balance

information is independent of the average output current

information used for positioning as described in the Output

Current Sensing section.

The magnitude of the internal ramp can be set to optimize

the transient response of the system. It also monitors the

supply voltage for feed−forward control for changes in the

supply. A resistor connected from the power input voltage

to the RAMPADJ pin determines the slope of the internal

PWM ramp.

The balance between the phases can be programmed using

the I

C Phase Bal SW(x) commands (0xE3 to 0xEA).

This allows each phase to be adjusted if there is a

difference in temperature due to layout and airflow

considerations. The phase balance can be adjusted from a

default gain of 5 (Bits 4:0 = 10000). The minimum gain

programmable is 3.75 (Bits 4:0 = 00000) and the maximum

gain is 6.25 (Bits 4:0 = 11111).

Voltage Control Mode

A high gain, high bandwidth, voltage mode error

amplifier is used for the voltage mode control loop. The

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NCP4208MNR2G

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