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NCP4208MNR2G

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NCP4208
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16
I
2
C Interface
Control of the NCP4208 is carried out using the I
2
C
Interface. The NCP4208 SMBus address is 0x20
(010 0000). With the R/W
bit set to 0 this gives an 8 bit
address of 0x40.
Data is sent over the serial bus in sequences of nine clock
pulses: 8 bits of data followed by an acknowledge bit from
the slave device. Transitions on the data line must occur
during the low period of the clock signal and remain stable
during the high period, because a low−to−high transition
when the clock is high might be interpreted as a stop signal.
The number of data bytes that can be transmitted over the
serial bus in a single read or write operation is limited only
by what the master and slave devices can handle.
1. When all data bytes have been read or written, stop
conditions are established. In write mode, the
master pulls the data line high during the tenth
clock pulse to assert a stop condition. In read mode,
the master device overrides the acknowledge bit by
pulling the data line high during the low period
before the ninth clock pulse; this is known as No
Acknowledge. The master takes the data line low
during the low period before the tenth clock pulse,
and then high during the tenth clock pulse to assert
a stop condition.
Any number of bytes of data can be transferred over
the serial bus in one operation, but it is not possible
to mix read and write in one operation because the
type of operation is determined at the beginning and
cannot subsequently be changed without starting a
new operation.
In the NCP4208, write operations contain one, two
or three bytes, and read operations contain one or
two bytes. The command code or register address
determines the number of bytes to be read or written,
See the register map for more information.
To write data to one of the device data registers or
read data from it, the address pointer register must
be set so that the correct data register is addressed
(i.e. command code), and then data can be written to
that register or read from it. The first byte of a read
or write operation always contains an address that is
stored in the address pointer register. If data is to be
written to the device, the write operation contains a
second data byte that is written to the register
selected by the address pointer register.
This write byte operation is shown in Figure 12. The
device address is sent over the bus, and then R/
W is
set to 0. This is followed by two data bytes. The first
data byte is the address of the internal data register
to be written to, which is stored in the address
pointer register. The second data byte is the data to
be written to the internal data register.
2. The read byte operation is shown in Figure 13. First
the command code needs to be written to the
NCP4208 so that the required data is sent back.
This is done by performing a write to the NCP4208
as before, but only the data byte containing the
register address is sent, because no data is written to
the register. A repeated start is then issued and a
read operation is then performed consisting of the
serial bus address; R/
W bit set to 1, followed by the
data byte read from the data register.
Figure 11. Send Byte
R/W
0
SCL
SDA
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
START BY MASTER
FRAME 1
SERIAL BUS ADDRESS
BYTE
FRAME 2
COMMAND CODE
1
1
ACK. BY NCP4208
9
9
10
Figure 12. Write Byte
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
NCP4208
STOP BY
MASTER
1
9
SCL (CONTINUED)
SDA (CONTINUED)
FRAME 3
DATA
BYTE
R/W
0
SCL
SDA
1
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
NCP4208
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS
BYTE
FRAME 2
COMMAND CODE
1
1
ACK. BY
NCP4208
9
0
9
ACK. BY NCP4208
STOP B
Y
MASTER
NCP4208
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17
Figure 13. Read Byte
R/W
0
SCL
SDA
1 0000 D7
D6
D5
D4
D3
D2
D1
D0
NO ACK. BY
MASTER
REPEATED START
BY MASTER
FRAME 1
SERIAL BUS ADDRESS
BYTE
1
1
ACK. BY
NCP4208
9
0
9
FRAME 2
DATA BYTE
FROM NCP4208
R/W
0
SCL
SDA 0 0 0 0
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
NCP4208
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS
BYTE
FRAME 2
COMMAND CODE
1
1
ACK. BY
NCP4208
9
9
10
STOP B
Y
MASTER
3. It is not possible to read or write a data byte from a
data register without first writing to the address
pointer register, even if the address pointer register
is already at the correct value.
4. In addition to supporting the send byte, the
NCP4208 also supports the read byte, write byte,
read word and write word protocols.
Write Operations
The following abbreviations are used in the diagrams:
S—START
P—STOP
R—READ
W—WRITE
A—ACKNOWLEDGE
A
—NO ACKNOWLEDGE
The NCP4208 uses the following I
2
C write protocols.
Send Byte
In this operation, the master device sends a single
command byte to a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7−bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA and
the transaction ends.
For the NCP4208, the send byte protocol is used to clear
Faults. This operation is shown in Figure 14.
Figure 14. Send Byte Command
SLAVE
ADDRESS
COMMAND
CODE
AAWSP
246531
If the master is required to read data from the register
immediately after setting up the address, it can assert a repeat
start condition immediately after the final ACK and carry
out a single byte read without asserting an intermediate stop
condition.
Write Byte
In this operation, the master device sends a command byte
and one data byte to the slave device as follows: The master
device asserts a start condition on SDA.
1. The master sends the 7−bit slave address followed
by the write bit (low).
2. The addressed slave device asserts ACK on SDA.
3. The master sends a command code.
4. The slave asserts ACK on SDA.
5. The master sends a data byte.
6. The slave asserts ACK on SDA.
7. The master asserts a stop condition on SDA and
the transaction ends.
The byte write operation is shown Figure 15.
Figure 15. Single Byte Write to a Register
SLAVE
ADDRESS
COMMAND
CODE
DATAAAWSA
2465317
P
8
Write Word
In this operation, the master device sends a command byte
and two data bytes to the slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7−bit slave address followed
by the write bit (low).
NCP4208
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3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends the first data byte.
7. The slave asserts ACK on SDA.
8. The master sends the second data byte.
9. The slave asserts ACK on SDA.
10. The master asserts a stop condition on SDA and
the transaction ends.
The word write operation is shown in Figure 16.
Figure 16. Single Word Write to a Register
SLAVE
ADDRESS
COMMAND
CODE
DATA
(LSB)
AAWSAP
24653178
DATA
(MSB)
A
109
Block Write
In this operation, the master device sends a command byte
and a byte count followed by the stated number of data bytes
to the slave device as follows:
1. The master device asserts a START condition on
SDA.
2. The master sends the 7−bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends the byte count N
7. The slave asserts ACK on SDA.
8. The master sends the first data byte
9. The slave asserts ACK on SDA.
10. The master sends the second data byte.
11. The slave asserts ACK on SDA.
12. The master sends the remainder of the data byes.
13. The slave asserts an ACK on SDA after each data
byte.
14. After the last data byte the master asserts a STOP
condition on SDA.
Figure 17. Block Write to a Register
SLAVE
ADDRESS
COMMAND
CODE
DATA
BYTE 1
AAWS
24653178
9
BYTE COUNT
= N
AA
...
10
DATA
BYTE 2
A
...
DATA
BYTE N
PA
11 12 13 14
Read Operations
The NCP4208 uses the following I
2
C read protocols.
Read Byte
In this operation, the master device receives a single byte
from a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7−bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserted ACK on SDA.
6. The master sends a repeated start condition on
SDA.
7. The master sends the 7 bit slave address followed
by the read bit (high).
8. The slave asserts ACK on SDA.
9. The slave sends the Data Byte.
10. The master asserts NO ACK on SDA.
11. The master asserts a stop condition on SDA and
the transaction ends.
Figure 18. Single Byte Read from a Register
SLAVE
ADDRESS
COMMAND
CODE
DATAAAWSA
2465317
8
S
SLAVE
ADDRESS
AR
10
9 11
P
Read Word
In this operation, the master device receives two data
bytes from a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7−bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserted ACK on SDA.
6. The master sends a repeated start condition on SDA.
7. The master sends the 7 bit slave address followed
by the read bit (high).
8. The slave asserts ACK on SDA.
9. The slave sends the first Data Byte (low Data Byte).
10. The master asserts ACK on SDA.
11. The slave sends the second Data Byte (high Data
Byte).
12. The masters asserts a No ACK on SDA
13. The master asserts a stop condition on SDA and
the transaction ends.
Figure 19. Word Read from a Command Coder
SLAVE
ADDRESS
COMMAND
CODE
DATA
(LSB)
AAWSA
24653178
S
SLAVE
ADDRESS
AR
109
DATA
(MSB)
AP
1211 13
In this operation, the master device sends a command
byte, the slave sends a byte count followed by the stated
number of data bytes to the master device as follows:
1. The master device asserts a START condition on
SDA.
2. The master sends the 7−bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a REPEATED START condition
on SDA.
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NCP4208MNR2G

Mfr. #:
Buy NCP4208MNR2G
Manufacturer:
ON Semiconductor
Description:
Switching Controllers VR11.1 8PH CTRL PMBUS ITF
Lifecycle:
New from this manufacturer.
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