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NCP4208MNR2G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
NCP4208
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4
ABSOLUTE MAXIMUM RATINGS
Rating Symbol Value Unit
Input Voltage Range V
IN
−0.3 to 6 V
FBRTN V
FBRTN
−0.3 to +0.3 V
PWM2 to PWM8, Rampadj −0.3 to V
IN
+ 0.3 V
SW1 to SW8 −5 to +25 V
SW1 to SW8 (<200 ns) −10 to +25 V
All other Inputs and Outputs −0.3 to V
IN
+ 0.3 V
Storage Temperature Range TSTG −65 to 150 °C
Operating Ambient Temperature Range 0 to 85 °C
ESD Capability, Human Body Model ESDHBM 1.5 kV
ESD Capability, Machine Model ESDMM 150 V
Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions (Note 2)
T
SLD
260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
1. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
THERMAL CHARACTERISTICS
Rating Symbol Value Unit
Thermal Resistance, Junction−to−Air (Note 2)
QFN, 7x7 mm
R
q
JA
27 °C/W
2. Values based on copper area of 645 mm
2
(or 1 in
2
) of 1 oz copper thickness and FR4 PCB substrate.
Figure 3. NCP4208 RT vs Frequency
TYPICAL CHARACTERISTICS
0
500
1000
1500
2000
2500
0 100 200 300 400 500 600 700 800 900
RT (kW)
Frequency (kHz)
PWM1
NCP4208
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5
PIN ASSIGNMENT
Pin No. Mnemonic Description
1 VCC3 3.3 V Power Supply Output. A capacitor from this pin to ground provided decoupling for the
interval 3.3 V LDO.
2 PWRGD Power−Good Output: Open−drain output that signals when the output voltage is outside of the
proper operating range.
3 ALERT ALERT Output: Open drain output that asserts low when the VR exceeds a programmable limit.
Can be configured for Comparator Mode or Interrupt Mode.
4 SDA Digital Input / Output. I
2
C serial data bidirectional pin. Requires pullup.
5 SCL Digital Input. I
2
C serial bus clock open drain input. Requires pullup.
6 EN Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the
PWRGD output low.
7 GND Ground. All internal biasing and the logic output signals of the device are referenced to this
ground.
8 to 9 NC No Connect
10 IMON Total Current Output Pin.
11 IREF Current Reference Input. An external resistor from this pin to ground sets the reference current for
IFB, and IILIMFS.
12 RT Frequency Setting Resistor Input. An external resistor connected between this pin and GND
sets the oscillator frequency of the device.
13 RAMPADJ PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets
the internal PWM ramp.
14 FBRTN Feedback Return. VID DAC and error amplifier reference for remote sensing of the output
voltage.
15 COMP Error Amplifier Output and Compensation Point.
16 FB Feedback Input. Error amplifier input for remote sensing of the output voltage. An external
resistor between this pin and the output voltage sets the no load offset point.
17 CSREF Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the
current sense amplifier and the power−good and crowbar functions. This pin should be
connected to the common point of the output inductors.
18 CSSUM Current Sense Summing Node. External resistors from each switch node to this pin sum the
average inductor currents together to measure the total output current.
19 CSCOMP Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM
determines the gain of the current sense amplifier and the positioning loop response time.
20 ILIMFS Current Sense and Limit Scaling Pin. An external resistor from this pin to CSCOMP sets the
internal current sensing signal for current limit and IMON. This value can be overwritten using
the I
2
C interface.
21 ODN Output Disable Logic Output for PSI operation. This pin is actively pulled low when PSI is low,
otherwise it functions in the same way as OD1
.
22 OD1 Output Disable Logic Output. This pin is actively pulled low when the EN input is low or when
VCC is below its UVLO threshold to signal to the Driver IC that the driver high−side and
low−side outputs should go low.
23 to 30 SW8 to SW1 Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of
unused phases should be left open.
31 to 38 PWM8 to PWM1 Logic−Level PWM Outputs. Each output is connected to the input of an external MOSFET driver
such as the ADP3121. Connecting the PWM8, PWM7, PWM6, PWM5, PWM4, PWM3 and
PWM2 outputs to VCC causes that phase to turn off, allowing the NCP4208 to operate as a
1−, 2−, 3−, 4−, 5−, 6−, 7−, or 8−phase controller.
39 VCC
Supply Voltage for the Device. A 340 W resistor should be placed between the 12 V system
supply and the VCC pin. The internal shunt regulator maintains VCC = 5.0 V.
40 to 47 VID7 to VID0 Voltage Identification DAC Inputs. These eight pins are pulled down to GND, providing a logic
zero if left open. When in normal operation mode, the DAC output programs the FB regulation
voltage from 0.375 V to 1.6 V.
48 PSI Power State Indicator. Pulling this pin low places the controller in lower power state operation.
NCP4208
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6
ELECTRICAL CHARACTERISTICS
V
IN
= (5.0 V) FBRTN − GND, for typical values T
A
= 25°C, for min/max values T
A
= 0°C to 85°C; unless otherwise noted. (Notes 1 and 2)
Parameter
Test Conditions Symbol Min Typ Max Unit
Reference Current
Reference Bias Voltage V
IREF
1.75 1.8 1.85 V
Reference Bias Current
R
IREF
= 121 kW
I
IREF
15
mA
Error Amplifier
Output Voltage Range V
COMP
0 4.4 V
Accuracy Relative to nominal DAC output, referenced
to FBRTN (refer to Figure 4)
In startup
V
FB
V
FB(BOOT)
−9.0
1.091
1.1
+9.0
1.109
mV
V
Load Line Positioning Accuracy −77 −80 −83 mV
Load Line Range −350 0 mV
Load Line Attenuation 0 100 %
Differential Non−linearity −1.0 +1.0 LSB
Input Bias Current I
FB
= I
IREF
I
FB
13.3 15 18.5
mA
Offset Accuracy VR Offset Register = 111111, VID = 1.0 V
VR Offset Register = 011111, VID = 1.0 V
−193.75
193.75
mV
FBRTN Current I
FBRTN
100 200
mA
Output Current FB forced to V
OUT
−3% I
COMP
500
mA
Gain Bandwidth Product COMP = FB GBW
(ERR)
20 MHz
Slew Rate COMP = FB 25
V/ms
BOOT Voltage Hold Time Internal Timer t
BOOT
2.0 ms
VID Inputs
Input Low Voltage
Input High Voltage
VID(X) V
IL(VID)
V
IH(VID)
0.8
0.3 V
Input Current I
IN(VID)
−5.0
mA
VID Transition Delay Time VID code change to FB change 400 ns
No CPU Detection Turn−Off Delay
Time
VID code change to PWM going low 5.0
ms
Oscillator
Frequency Range f
OSC
0.25 9.0 MHz
Frequency Variation
T
A
= 25°C, R
T
= 500 kW, 4−phase
T
A
= 25°C, R
T
= 250 kW, 4−phase
T
A
= 25°C, R
T
= 121 kW, 4−phase
f
PHASE
170 195
375
750
225 kHz
Output Voltage
RT = 500 kW to GND
V
RT
1.9 2.01 2.1 V
RAMPADJ Output Voltage RAMPADJ − FB, V
FB
= 1.0 V,
IRAMPADJ = −150 mA
V
RAMPADJ
−50 +50 mV
RAMPADJ Input Current Range I
RAMPADJ
5.0 60
mA
Current Sense Amplifier
Offset Voltage CSSUM − CSREF (refer to Figure 5) V
OS(CSA)
−1.0 +1.0 mV
Input Bias Current, CSREF CSREF = 1.0 V I
BIAS(CSREF)
−20 +20
mA
Input Bias Current, CSSUM CSREF = 1.0 V I
BIAS(CSSUM)
−10 +10 nA
Gain Bandwidth Product CSSUM = CSCOMP GBW
(CSA)
10 MHz
Slew Rate C
CSCOMP
= 10 pF 10
V/ms
Input Common−Mode Range CSSUM and CSREF 0 3.0 V
Output Voltage Range 0.05 3.0 V
Output Current I
CSCOMP
500
mA
Current Limit Latchoff Delay Time Internal Timer 8.0 ms
1. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T
J
= T
A
= 25_C. Low
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
2. Refer to Application Information section.
3. Values based on design and/or characterization.
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NCP4208MNR2G

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Buy NCP4208MNR2G
Manufacturer:
ON Semiconductor
Description:
Switching Controllers VR11.1 8PH CTRL PMBUS ITF
Lifecycle:
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