UDA1351H/N1,551 Datasheet UDA1351H/N1,551, UDA1351H/N1,557 | P16-P18

2000 Jul 27 16

Philips Semiconductors Product speciﬁcation

96 kHz IEC 958 audio DAC UDA1351H

8.7 L3 interface

8.7.1 GENERAL

The UDA1351H has an L3 microcontroller interface and all

the digital sound processing features and various system

settings can be controlled by a microcontroller.

The controllable settings are:

• Restoring L3 defaults

• Power-on

• Selection of input channel, clock source, DAC input and

external input format

• Selection of filter mode and settings of treble and bass

boost

• Volume settings

• Selection of soft mute via cosine roll-off (only effective in

L3 control mode) and bypass of auto mute

• Selection of de-emphasis.

The readable settings are:

• Mute status of interpolator

• PLL locked

• SPDIF input signal locked

• Audio Sample Frequency (ASF)

• Valid PCM data detected

• Pre-emphasis of the IEC 958 input signal

• ACcuracy of the Clock (ACC).

The exchange of data and control information between the

microcontroller and the UDA1351H is LSB first and is

accomplished through a serial hardware L3 interface

comprising the following pins:

• L3DATA: data line

• L3MODE: mode line

• L3CLK: clock line.

The exchange of bytes via the L3 interface is LSB first.

The L3 format has 2 modes of operation:

• Address mode

• Data transfer mode.

The address mode is used to select a device for a

subsequent data transfer. The address mode is

characterized by L3MODE being LOW and a burst of

8 pulses on L3CLOCK, accompanied by 8 bits (see Fig.7).

The data transfer mode is characterized by L3MODE

being HIGH and is used to transfer one or more bytes

representing a register address, instruction or data.

Basically 2 types of data transfers can be defined:

• Write action: data transfer to the device

• Read action: data transfer from the device.

Remark: when the device is powered up, at least one

L3CLOCK pulse must be given to the L3 interface to

wake-up the interface before starting sending to the device

(see Fig.7). This is only needed once after the device is

powered up.

8.7.2 DEVICE ADDRESSING

The device address consists of 1 byte with:

• Bits 0 and 1 (called DOM bits) representing the type of

data transfer (see Table 5)

• Bits 2 to 7 (address bits) representing a 6-bit device

address.

Table 5 Selection of data transfer

8.7.3 REGISTER ADDRESSING

After sending the device address, including Data

Operating Mode (DOM) bits indicating whether the

information is to be read or written, 1 data byte is sent

using bit 0 to indicate whether the information will be read

or written and bits 1 to 7 for the destination register

address.

Basically there are 3 methods for register addressing:

1. Addressing for write data: bit 0 is logic 0 indicating

a write action to the destination register, followed by

bits 1 to 7 indicating the register address (see Fig.7)

2. Addressing for prepare read: bit 0 is logic 1 indicating

that data will be read from the register (see Fig.8)

3. Addressing for data read action: in this case the device

returns a register address prior to sending data from

that register. When bit 0 is logic 0, the register address

is valid; in case bit 0 is logic 1 the register address is

invalid.

DOM

TRANSFER

BIT 0 BIT 1

0 0 not used

1 0 not used

0 1 write data or prepare read

1 1 read data

2000 Jul 27 17

Philips Semiconductors Product speciﬁcation

96 kHz IEC 958 audio DAC UDA1351H

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MGS753

L3CLOCK

L3MODE

L3DATA

write

L3 wake-up pulse after power-up

device address

DOM bits

data byte 1 data byte 2

Fig.7 Data write mode (for L3 version 2).

MGS754

L3CLOCK

L3MODE

L3DATA

read

valid/non-valid

device address

prepare read send by the device

DOM bits

data byte 1 data byte 2

111

0/1

Fig.8 Data read mode.

2000 Jul 27 18

Philips Semiconductors Product speciﬁcation

96 kHz IEC 958 audio DAC UDA1351H

8.7.4 DATA WRITE MODE

The data write mode is explained in the signal diagram

of Fig.7. For writing data to a device, 4 bytes must be sent

(see Table 6):

1. One byte starting with ‘01’ for signalling the write

action to the device, followed by the device address

(‘011000’ for the UDA1351H)

2. One byte starting with a ‘0’ for signalling the write

action, followed by 7 bits indicating the destination

address in binary format with A6 being the MSB and

A0 being the LSB

3. Two data bytes with D15 being the MSB and D0 being

the LSB.

Remark: each time a new destination register address

needs to be written, the device address must be sent

again.

8.7.5 DATA READ MODE

For reading data from the device, first a prepare read must

be done and then data read. The data read mode is

explained in the signal diagram of Fig.8.

For reading data from a device, the following 6 bytes are

involved (see Table 7):

1. One byte with the device address including ‘01’ for

signalling the write action to the device

2. One byte is sent with the register address from which

data needs to be read; this byte starts with a ‘1’, which

indicates that there will be a read action from the

address in binary format with A6 being the MSB and

A0 being the LSB

3. One byte with the device address including ‘11’ is sent

to the device; the ‘11’ indicates that the device must

write data to the microcontroller

4. One byte, sent by the device to the bus, with the

(requested) register address and a flag bit indicating

whether the requested register was valid (bit is logic 0)

or invalid (bit is logic 1)

5. Two bytes, sent by the device to the bus, with the data

information in binary format with D15 being the MSB

and D0 being the LSB.

Table 6 L3 write data

Table 7 L3 read data

BYTE L3 MODE ACTION

FIRST IN TIME LATEST IN TIME

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

1 address device address 01011000

2 data transfer register address 0 A6 A5 A4 A3 A2 A1 A0

3 data transfer data byte 1 D15 D14 D13 D12 D11 D10 D9 D8

4 data transfer data byte 2 D7 D6 D5 D4 D3 D2 D1 D0

BYTE L3 MODE ACTION

FIRST IN TIME LATEST IN TIME

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

1 address device address 01011000

2 data transfer register address 1 A6 A5 A4 A3 A2 A1 A0

3 address device address 11011000

4 data transfer register address 0 or 1 A6 A5 A4 A3 A2 A1 A0

5 data transfer data byte 1 D15 D14 D13 D12 D11 D10 D9 D8

6 data transfer data byte 2 D7 D6 D5 D4 D3 D2 D1 D0

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36

UDA1351H/N1,551

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IC DAC/AUDIO 24BIT 100K 44PQFP

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UDA1351H/N1,551

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