2000 Jul 27 22
Philips Semiconductors Product specification
96 kHz IEC 958 audio DAC UDA1351H
8.7.8.9 Bass boost
A 4-bit value to program the bass boost setting in
combination with the filter mode settings. At f
s
= 44.1 kHz
the 3 dB point for minimum setting is 250 Hz and the
3 dB point for maximum setting is 300 Hz. The default
value is ‘0000’.
Table 17 Bass boost settings
8.7.8.10 De-emphasis
A 2-bit value to enable the digital de-emphasis filter.
Table 18 De-emphasis selection
8.7.8.11 Soft mute
A 1-bit value to enable the digital mute.
Table 19 Soft mute selection
8.7.8.12 Volume control
A 6-bit value to program the left and right channel volume
attenuation. The range is from 0 to 60 dB and −∞ dB in
steps of 1 dB.
Table 20 Volume settings
BB3 BB2 BB1 BB0
LEVEL
FLAT
(dB)
MIN.
(dB)
MAX.
(dB)
0000000
0001022
0010044
0011066
0100088
010101010
011001212
011101414
100001616
100101818
101001820
101101822
110001824
110101824
111001824
111101824
DE1 DE0 FUNCTION
0 0 other (default setting)
01f
s
= 32.0 kHz
10f
s
= 44.1 kHz
11f
s
= 48.0 kHz
MT FUNCTION
0 no muting
1 muting (default setting)
VC5 VC4 VC3 VC2 VC1 VC0 VOLUME (dB)
000000 0
000001 0
000010 1
000011 2
:::::: :
110011 51
110100
110101 52
110110
110111 54
111000
111001 57
111010
111011
111100 60
111101
111110 −∞
111111
2000 Jul 27 23
Philips Semiconductors Product specification
96 kHz IEC 958 audio DAC UDA1351H
8.7.8.13 Auto mute
A 1-bit value to activate mute during out-of-lock. In normal
operation the output is automatically hard muted when an
out-of-lock situation is detected. Setting this bit to logic 0
will disable that function.
Table 21 Auto mute setting
8.7.8.14 PLL reset
A 1-bit value to reset the PLL. This is the bit which is set in
the initialization string. When this bit is asserted, the PLL
will be reset and the output clock of the PLL will be forced
to its lowest value, which is in the area of a few MHz.
Table 22 PLL reset
8.7.9 READABLE REGISTERS
8.7.9.1 Mute status
A 1-bit value indicating whether the interpolator is muting
or not muting.
Table 23 Interpolator mute status
8.7.9.2 PLL lock detection
A 1-bit value indicating that the clock regeneration is
locked.
Table 24 PLL lock indication
8.7.9.3 SPDIF lock detection
A 1-bit value indicating the IEC 958 decoder is locked and
is decoding correct data.
Table 25 SPDIF lock detection
8.7.9.4 Audio sample frequency detection
A 2-bit value indicating the audio sample frequency of the
IEC 958 input signal.
Table 26 Audio sample frequency detection
Auto MT FUNCTION
0 do not mute output during out-of-lock
1 mute output during out-of-lock
(default setting)
RST PLL FUNCTION
0 normal operation (default)
1 PLL is reset
MT stat FUNCTION
0 no muting
1 muting
PLL lock FUNCTION
0 out-of-lock
1 locked
SPD lock FUNCTION
0 not locked or non-PCM data detected
1 locked and PCM data detected
ASF1 ASF0 FUNCTION
0 0 44.1 kHz
0 1 undefined
1 0 48.0 kHz
1 1 32.0 kHz
2000 Jul 27 24
Philips Semiconductors Product specification
96 kHz IEC 958 audio DAC UDA1351H
8.7.9.5 PCM detection
A 1-bit value which indicates whether the IEC 958 input
contains PCM audio data or other binary data.
Table 27 Two-channel PCM input detection
8.7.9.6 Pre-emphasis detection
A 1-bit value which indicates whether the pre-emphasis bit
was set on the IEC 958 input signal or not set.
Table 28 Pre-emphasis detection
8.7.9.7 Clock accuracy detection
A 2-bit value indicating the timing accuracy of the IEC 958
input signal is conforming to the IEC 958 specification.
Table 29 Input signal accuracy detection
PCM stat FUNCTION
0 input with 2 channel PCM data
1 input without 2 channel PCM data
PRE FUNCTION
0 no pre-emphasis
1 pre-emphasis
ACC1 ACC0 FUNCTION
0 0 level II
01levelI
1 0 level III
1 1 undefined
9 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
Notes
1. All V
DD
and V
SS
connections must be made to the same power supply.
2. JEDEC class 2 compliant, except pin V
SSA(PLL)
which can withstand ESD pulses of 1600 to +1600 V.
3. Latch-up test at T
amb
= 125 °C and V
DD
= 3.6 V.
4. Short-circuit test at T
amb
=0°C and V
DD
= 3 V. DAC operation after short-circuiting cannot be warranted.
10 THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DD
supply voltage note 1 2.7 5.0 V
T
xtal
crystal temperature 25 +150 °C
T
stg
storage temperature 65 +125 °C
T
amb
ambient temperature 40 +85 °C
V
es
electrostatic handling voltage Human Body Model (HBM); note 2 2000 +2000 V
Machine Model (MM) 200 +200 V
I
lu(prot)
latch-up protection current note 3 200 mA
I
sc(DAC)
short-circuit current of DAC note 4
output short-circuited to V
SSA(DAC)
482 mA
output short-circuited to V
DDA(DAC)
346 mA
SYMBOL PARAMETER CONDITIONS VALUE UNIT
R
th(j-a)
thermal resistance from junction to ambient in free air 63 K/W

UDA1351H/N1,551

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC DAC/AUDIO 24BIT 100K 44PQFP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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