M41T66Q6F Datasheet M41T66Q6F | P19-P21

M41T66 Clock operation

Doc ID 15108 Rev 2 19/34

3.4 Watchdog timer

The watchdog timer can be used to detect an out-of-control microprocessor. The user

programs the watchdog timer by setting the desired amount of time-out into the Watchdog

Bits BMB4-BMB0 store a binary multiplier and the three bits RB2-RB0 select the resolution

where:

000=1/16 second (16Hz)

001=1/4 second (4Hz)

010=1 second (1Hz)

011=4 seconds (1/4Hz) and

100 = 1 minute (1/60Hz)

Note: Invalid combinations (101, 110, and 111) will NOT enable a watchdog time-out. Setting the

BMB4-BMB0 = 0 with any combination of RB2-RB0, other than 000, will result in an

immediate watchdog time-out.

The amount of time-out is then determined to be the multiplication of the five-bit multiplier

value with the resolution. (For example: writing 00001110 in the watchdog register = 3*1 or 3

seconds). If the processor does not reset the timer within the specified period, the M41T66

sets the WDF (watchdog flag) and generates an interrupt on the IRQ

/OUTpin. The

watchdog timer can only be reset by having the microprocessor perform a WRITE of the

watchdog register. The time-out period then starts over.

Should the watchdog timer time-out, any value may be written to the watchdog register in

order to clear the IRQ

/OUT pin. A value of 00h will disable the watchdog function until it is

again programmed to a new value. A READ of the flags register will reset the watchdog flag

(bit D7; register 0Fh). The watchdog function is automatically disabled upon power-up, and

the watchdog register is cleared.

Note: A WRITE to any clock register will restart the watchdog timer.

Clock operation M41T66

20/34 Doc ID 15108 Rev 2

3.5 Square wave output

The M41T66 offers the user a programmable square wave function which is output on the

SQW pin. RS3-RS0 bits located in 04h establish the square wave output frequency. These

frequencies are listed in Table 4. Once the selection of the SQW frequency has been

completed, the SQW pin can be turned on and off under software control with the square

wave enable bit (SQWE) located in register 0Ah.

The SQW output is an open drain output driver. The initial power-up default for the SQW

output is 32 KHz.

Note: When the SQW is enabled and the ST bit is set (ST = 1), the square wave output could be

low or high and could drain current through the pull-up resistor.

Due to the output buffer circuitry used for the SQW output, this pin must not be taken to a

voltage greater than V

. A diode is required on the SQW pin for SuperCap™ (or battery)

backup. A low threshold BAT42 diode is recommended (see Figure 4 on page 7).

3.6 Century bits

These two bits will increment in a binary fashion at the turn of the century, and handle all

leap years correctly. See Table 6 on page 22 for additional explanation.

Table 4. Square wave output frequency

Square wave bits Square wave

RS3 RS2 RS1 RS0 Frequency Units

0000None–

000132.768kHz

00108.192kHz

00114.096kHz

01002.048kHz

01011.024kHz

0110512Hz

0111256Hz

1000128Hz

100164Hz

101032Hz

101116Hz

11008Hz

11014Hz

11102Hz

11111Hz

M41T66 Clock operation

Doc ID 15108 Rev 2 21/34

3.7 Output driver pin

When the OFIE bit, AFE bit, and watchdog register are not set to generate an interrupt, the

IRQ

/OUT pin becomes an output driver that reflects the contents of D7 of the calibration

/OUT pin will be driven low.

Note: The IRQ

/OUT pin is an open drain which requires an external pull-up resistor.

3.8 Oscillator stop detection

If the oscillator fail (OF) bit is internally set to a '1,' this indicates that the oscillator has either

stopped, or was stopped for some period of time and can be used to judge the validity of the

clock and date data. This bit will be set to '1' any time the oscillator stops.

In the event the OF bit is found to be set to '1' at any time other than the initial power-up, the

STOP bit (ST) should be written to a '1,' then immediately reset to '0.' This will restart the

oscillator.

The following conditions can cause the OF bit to be set:

● The first time power is applied (defaults to a '1' on power-up).

● The voltage present on V

or battery is insufficient to support oscillation.

● The ST bit is set to '1.'

● External interference of the crystal

If the oscillator fail interrupt enable bit (OFIE) is set to a '1,' the IRQ

/OUTpin will also be

activated. The IRQ

/OUT output is cleared by resetting the OFIE or OF bit to '0' (NOT by

reading the flag register).

The OF bit will remain set to '1' until written to logic '0.' The oscillator must start and have

run for at least 1 second before attempting to reset the OF bit to '0.' If the trigger event

occurs during a power-down condition, this bit will be set correctly.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P34

M41T66Q6F

Mfr. #:

Buy M41T66Q6F

Manufacturer:

STMicroelectronics

Description:

Real Time Clock real-time clock with alarms

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet

M41T66Q6F