M41T66Q6F Datasheet M41T66Q6F | P7-P9

M41T66 Description

Doc ID 15108 Rev 2 7/34

Figure 4. Hardware hookup for SuperCap™ backup operation

1. Open drain

2. For a crystal with a load capacitance (C

) of 12.5 pF, two parallel external 12.5 pF capacitors (C

and C

)

must be added to achieve better clock accuracy.

3. It can also be connected to another power supply.

4. Due to the output buffer circuitry used for the SQW output, this pin must not be taken to a voltage greater

than V

. Diode required on SQW pin for SuperCap™ (or battery) backup. Low threshold BAT42 diode

recommended.

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Operation M41T66

8/34 Doc ID 15108 Rev 2

2 Operation

The M41T66 clock operates as a slave device on the serial bus. Access is obtained by

implementing a start condition followed by the correct slave address (D0h). The 16 bytes

contained in the device can then be accessed sequentially in the following order:

● 1

byte: tenths/hundredths of a second register

● 2

byte: seconds register

● 3

byte: minutes register

● 4

byte: hours register

● 5

byte: square wave/day register

● 6

byte: date register

● 7

byte: century/month register

● 8

byte: year register

● 9

byte: calibration register

● 10

byte: watchdog register

● 11

- 15

bytes: alarm registers

● 16

byte: flags register

2.1 2-wire bus characteristics

The bus is intended for communication between different ICs. It consists of two lines: a

bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must

be connected to a positive supply voltage via a pull-up resistor.

The following protocol has been defined:

● Data transfer may be initiated only when the bus is not busy.

● During data transfer, the data line must remain stable whenever the clock line is high.

● Changes in the data line, while the clock line is high, will be interpreted as control

signals.

Accordingly, the following bus conditions have been defined:

2.1.1 Bus not busy

Both data and clock lines remain high.

2.1.2 Start data transfer

A change in the state of the data line, from high to low, while the clock is high, defines the

START condition.

2.1.3 Stop data transfer

A change in the state of the data line, from low to high, while the clock is high, defines the

STOP condition.

M41T66 Operation

Doc ID 15108 Rev 2 9/34

2.1.4 Data valid

The state of the data line represents valid data when after a start condition, the data line is

stable for the duration of the high period of the clock signal. The data on the line may be

changed during the low period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a start condition and terminated with a stop condition.

The number of data bytes transferred between the start and stop conditions is not limited.

The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.

By definition a device that gives out a message is called “transmitter,” the receiving device

that gets the message is called “receiver.” The device that controls the message is called

“master.” The devices that are controlled by the master are called “slaves.”

2.1.5 Acknowledge

Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low

level put on the bus by the receiver whereas the master generates an extra acknowledge

related clock pulse. A slave receiver which is addressed is obliged to generate an

acknowledge after the reception of each byte that has been clocked out of the slave

transmitter.

The device that acknowledges has to pull down the SDA line during the acknowledge clock

pulse in such a way that the SDA line is a stable low during the high period of the

acknowledge related clock pulse. Of course, setup and hold times must be taken into

account. A master receiver must signal an end of data to the slave transmitter by not

generating an acknowledge on the last byte that has been clocked out of the slave. In this

case the transmitter must leave the data line high to enable the master to generate the

STOP condition.

Figure 5. Serial bus data transfer sequence

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M41T66Q6F

Mfr. #:

Buy M41T66Q6F

Manufacturer:

STMicroelectronics

Description:

Real Time Clock real-time clock with alarms

Lifecycle:

New from this manufacturer.

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M41T66Q6F