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LTC4211CMS#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40
LTC4211
16
4211fc
For more information www.linear.com/LTC4211
OPERATION
a start-up check to make sure the supply voltage is above
its 2.3V UVLO threshold (see Time Point 1). If the input
supply voltage is valid, the gate of the external pass tran
-
sistor is pulled to ground by the internal 200µA current
source connected at the GATE pin. The TIMER pin is held
low by an internal N-channel pull-down transistor (see
M6, LTC4211 Block Diagram) and the FILTER pin voltage
is pulled to ground by an internal 10µA current source.
Once V
CC
and ON (the ON pin is >1.316) are valid, the
LTC4211 checks to make sure that GATE is OFF (V
GATE
<
0.2V) at Time Point 2. An internal timing circuit is enabled
and the TIMER pin voltage ramps up at the rate described by
Equation 1. At Time Point 3 (the timing period programmed
by C
TIMER
), the TIMER pin voltage equals V
TMR
(1.236V).
Next, the TIMER pin voltage ramps down to Time Point 4
where the LTC4211 performs two checks: (1) FILTER pin
voltage is low (V
FILTER
< 1.156V) and (2) FAULT pin volt-
age is high (V
FAULT
> 1.286V). If both conditions are met,
the LTC4211 begins a second timing (soft-start) cycle.
Second Timing (Soft-Start) Cycle
At the beginning of the second timing cycle (Time Point5),
the LTC4211’s FAST COMP is armed and an internal 10µA
current source working with an internal charge pump
provides the gate drive to the external pass transistor.
The
LTC4211 automatically limits the inrush current in one of
two ways: by controlling the GATE pin voltage slew rate
or by actively limiting the inrush current. If GATE voltage
slew rate control is preferred, an external capacitor C
GATE
can be used from GATE to ground, as shown in Figure 6.
An expression for the GATE voltage slew rate is given by
Equation 3:
V
GATE
Slew Rate,
dV
GATE
dt
=
10µA
C
GATE
(3)
Adding C
GATE
slows the GATE voltage slew rate at the ex-
pense of slower system turn-on and turn-off time. Should
this technique be used, values for C
GATE
less than 150nF
are recommended.
The inrush current being delivered to the load while
the GATE is ramping is dependent on C
LOAD
and C
GATE
.
Equation 4 gives an expression for the inrush current
during the second timing cycle:
I
INRUSH
=
dV
GATE
dt
• C
LOAD
= 10µA •
C
LOAD
C
GATE
(4)
For example, if C
GATE
= 3300pF and C
LOAD
= 2000µF, the
inrush current charging C
LOAD
is:
I
INRUSH
= 10µA •
2000µF
0.0033µF
= 6.06A
(5)
At Time Point 6, the output voltage trips COMP2’s thresh-
old, signaling an output voltage “power good” condition.
At T
ime Point 7,
RESET is asserted high, SLOW COMP is
armed and the LTC4211 enters a fault monitor mode. The
TIMER voltage then ramps down to Time Point 8.
Power-Off Cycle
As shown at Time Point 9, an external hard reset is initiated
by pulling the ON pin low (V
ON
< 1.236V). The GATE pin
voltage is ramped to ground by the internal 200µA cur-
rent source, discharging C
GATE
and turning off the pass
transistor. As C
LOAD
discharges, the output voltage crosses
COMP2’s threshold, signaling a “power bad” condition at
Time Point 10. At this point, RESET is asserted low.
Figure 6. Using an External Capacitor at GATE for
GATE Voltage Slew Rate Control
M1
Si4410DY
R
SENSE
0.007Ω
C
GATE
*
C
LOAD
4211 F06
+
V
CC
SENSE
LTC4211**
GATE
FB
R1
36k
V
OUT
5V
5A
V
IN
5V
R2
15k
*
**
VALUES ≤150nF SUGGESTED
ADDITIONAL DETAILS OMITTED
FOR CLARITY
=
dV
GATE
dt
V
GATE
SLEW RATE CONTROL
10µA
C
GATE
( )
LTC4211
17
4211fc
For more information www.linear.com/LTC4211
OPERATION
SOFT-START WITH CURRENT LIMITING
During the second timing cycle, the inrush current was
described by Equation 4. Note that there is a one-to-one
correspondence in the inrush current to C
LOAD
. If the inrush
current is large enough to cause a voltage drop greater
than 50mV across the sense resistor, an internal servo
loop controls the operation of the 10µA current source at
the GATE pin to regulate the load current to:
I
LIMIT(SOFTSTART)
=
50mV
R
SENSE
(6)
For example, the inrush current is limited to 5A when
R
SENSE
= 0.01Ω.
In this fashion, the inrush current is controlled and C
LOAD
is charged up slowly during the soft-start cycle.
The timing diagram in Figure 7 illustrates the operation
of the LTC4211 in a normal power-up sequence with lim
-
ited inrush current as described by Equation 6. At Time
Point5, the GA
TE pin voltage begins to ramp and the power
MOSFET starts to charge C
LOAD
. At Time Point 5A, the inrush
current causes a 50mV voltage drop across R
SENSE
and
the internal servo loop engages, limiting the inrush cur-
rent to a fixed level. At Time Point 6, the GATE pin voltage
continues to ramp as C
LOAD
charges until V
OUT
reaches its
final value. The charging current reduces, and the internal
servo loop disengages. At the end of the soft-start cycle
(Time Point 7), RESET is high and SLOW COMP is armed.
Figure 7. Normal Power-Up Sequence (with Current Limiting in Second Timing Cycle)
PLUG-IN CYCLE
FIRST TIMING CYCLE
TIMER
ON
V
CC
1 2 3 4 5 6 7 8 9
RESET PULLED LOW DUE TO POWER BAD
10
200µA
4211 F07
2µA2µA
V
REF
10µA
GATE
V
OUT
POWER BAD
V
FB
< V
REF
5A
SLOW COMPARATOR ARMEDCHECK FOR GATE < 0.2V
FAST COMPARATOR ARMED
CHECK FOR FILTER LOW (<V
REF
– 80mV)
CHECK FOR FAULT HIGH (>V
REF
+ 50mV)
ON GOES LOW
GATE
V
OUT
I
LOAD
RESET
SOFT-START CYCLE
SECOND TIMING CYCLE
POWER GOOD
V
FB
> V
REF
LOAD CURRENT IS
REGULATING AT 50mV/R
SENSE
LTC4211
18
4211fc
For more information www.linear.com/LTC4211
OPERATION
breaker if the voltage across the SENSE resistor (V
CC
–
V
SENSE
= V
CB
) is greater than 50mV for 20µs. There may
be applications where this comparator’s response time
is not long enough, for example, because of excessive
supply voltage noise. To adjust the response time of the
SLOW COMP, the MS version of the LTC4211 is chosen
and a capacitor is used at the LTC4211’s FILTER pin (see
section on Adjusting SLOW Comp’s Response Time). The
FAST COMP trips the circuit breaker to protect against fast
load overcurrents if the transient voltage across the sense
resistor is greater than 150mV for 300ns. The response
time of the LTC4211’s FAST COMP is fixed.
The timing diagram of Figure 7 illustrates when the
LTC4211’s electronic circuit breaker is armed. After the
first timing cycle, the LTC4211’s FAST COMP is armed
at Time Point 5. Arming FAST COMP at Time Point 5 en
-
sures that the system is protected against a short-circuit
condition during the second timing cycle. At Time Point 7,
SLOW COMP is armed when the internal control loop is
disengaged.
The timing diagrams in Figures 8 and 9 illustrate the op-
eration of the LTC4211 when the load current conditions
exceed the
thresholds of the FAST COMP (V
CB(FAST)
>
150mV) and SLOW COMP (V
CB(SLOW)
> 50mV), respec-
tively.
RESETTING THE ELECTRONIC CIRCUIT BREAKER
Once the
LTC4211’s circuit breaker is tripped, FAULT is
asserted low and the GATE pin is pulled to ground. The
LTC4211 remains latched OFF in this fault state until the
external fault is cleared. To clear the internal fault detect
circuitry and to restart the LTC4211, its ON pin must be
driven low (V
ON
< 1.236V) for at least 150µs, after which
time FAULT goes high. Toggling the ON pin from low to
high (V
ON
> 1.316V) initiates a restart sequence in the
LTC4211. The timing diagram in Figure 10 illustrates a
start-up sequence where the LTC4211 is powered up into
a load overcurrent condition. Note that the circuit breaker
trips at Time Point B and is reset at Time Point 9A.
FREQUENCY COMPENSATION AT SOFT-START
If the external gate capacitance is greater than 600pF, no
external gate capacitor is required at GATE to stabilize
the internal current-limiting loop during soft-start. Oth
-
erwise, connect a gate capacitor between the GATE pin
and ground to increase the total gate capacitance to be
equal to or above 600pF
. The servo loop that controls the
external MOSFET during current limiting has a unity-gain
frequency of about 105kHz and phase margin of 80° for
external MOSFET gate input capacitances to 2.5nF.
USING AN EXTERNAL GATE CAPACITOR
In addition to reducing the inrush current (Equation 4), an
external gate capacitor (Figure 6) may also be useful to
decrease or eliminate current spikes through the MOSFET
when power is first applied. At power-up, the instantaneous
input voltage step attempts to pull the MOSFET gate up
through the MOSFET’s drain-to-gate capacitance. If the
MOSFET’s C
GS
is small, the gate can be pulled up high
enough to turn on the MOSFET, thereby allowing a current
spike to the output. This event occurs during the time
that the LTC4211 is coming out of UVLO and getting its
intelligence to hold the GATE pin low. An external capaci
-
tor attenuates the voltage to which the GATE is pulled up
and eliminates the current spike. The value required is
dependent on the MOSFET capacitance specifications. In
typical applications, this capacitor is not required.
ELECTRONIC CIRCUIT BREAKER
The LT
C4211
features an electronic circuit breaker function
that protects against externally-generated fault conditions
and shorts or excessive load current and can also be con
-
figured to protect against input supply overvoltage. If the
cir
cuit breaker trips, the GA
TE pin is immediately pulled to
ground, the external N-channel MOSFET is quickly turned
OFF and FAULT is latched low.
The circuit breaker trips whenever the voltage across the
sense resistor exceeds two different levels, set by the
LTC4211’s SLOW COMP and FAST COMP thresholds
(see Block Diagram). The SLOW COMP trips the circuit
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LTC4211CMS#PBF

Mfr. #:
Buy LTC4211CMS#PBF
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers Hot Swap Controller w/Active Limit
Lifecycle:
New from this manufacturer.
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