Sensors
28 NXP Semiconductors
MMA16xx
3.7 Overload Response
3.7.1 Overload Performance
The device is designed to operate within a specified range. However, acceleration beyond that range (overload) impacts the
operating range output of the sensor. Acceleration beyond the range of the device can generate a DC shift at the output of the
device that is dependent upon the overload frequency and amplitude. The device g-cell is overdamped, providing the optimal
design for overload performance. However, the performance of the device during an overload condition is affected by many other
parameters, including:
g-cell damping
Non-linearity
Clipping limits
Symmetry
Figure 22 shows the g-cell, Sigma Delta, and output clipping of the device over frequency. The relevant parameters are
specified in Section 2.
Figure 22. Output Clipping Vs. Frequency
3.7.2 Sigma Delta Overrange Response
Overrange conditions exist when the signal level is beyond the full-scale range of the device but within the computational limits
of the DSP. The ΣΔ converter can saturate at levels above those specified in Section 2 (G
ADC_CLIP
). The DSP operates
predictably under all cases of overrange, although the signal may include residual high frequency components for some time after
returning to the normal range of operation due to non-linear effects of the sensor.
5kHz f
g-Cell
f
LPF
g
ADC_Clip
g
g-cell_Clip
Determined by g-cell
10kHz
g-cell
Rolloff
Acceleration (g)
Frequency (kHz)
LPF
Rolloff
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Region of No Signal Distortion Beyond
Specification
Region of Interest
roll-off and ADC clipping
g
Range_Norm
Determined by g-cell
roll-off and full-scale range
Region Clipped
by Output
Sensors
NXP Semiconductors 29
MMA16xx
4 DSI Protocol Layer
4.1 Communication Interface Overview
The device is compatible with the DSI Bus Standard V2.5.
4.1.1 DSI Physical Layer
Reference DSI Bus Standard V2.5, Section 3 for information regarding the physical layer.
4.1.2 DSI Data Link Layer
Reference DSI Bus Standard,V2.5, Section 4 for information regarding the DSI data link layer. The sections below describe
the DSI data link layer features supported.
4.2 DSI Protocol
4.2.1 DSI Bus Commands
DSI Bus Commands are summarized in Table 12. The device supports only the command formats specified in Section 4.2.1.
The device will ignore commands of any other format. If a CRC error is detected, or a reserved or un-implemented command is
received, the device will not respond.
Following all messages, the device requires a minimum inter-frame separation (t
IFS
). As long as the minimum inter-frame
separation times defined in Section 4.2.1 are met, all supported commands are guaranteed to be executed, and the device will
be ready for the next message. The device will respond as appropriate during the subsequent DSI transfer. Exactly one response
is attempted.
Table 12. DSI Bus Command Summary
Command Command Format Data
C3 C2 C1 C0 Hex Description D7 D6 D5 D4 D3 D2 D1 D0
0000$0Initialization Standard Long Only NV BSBnk[1]Bnk[0]PA[3]PA[2]PA[1]PA[0]
0001$1Request Status Standard/Enhanced L/S⎯⎯⎯⎯⎯⎯⎯⎯
0010$2Read Acceleration DataStandard/Enhanced L/S⎯⎯⎯⎯⎯⎯⎯⎯
0011$3Not Implemented Not Implemented Not Implemented
0100$4Request ID InformationStandard/Enhanced L/S⎯⎯⎯⎯⎯⎯⎯⎯
0101$5Not Implemented Not Implemented Not Implemented
0110$6Not Implemented Not Implemented Not Implemented
0111$7Clear Standard/Enhanced L/S⎯⎯⎯⎯⎯⎯⎯⎯
1000$8Not Implemented Not Implemented Not Implemented
1001$9Read Write NVM Standard/Enhanced LWA[3]WA[2]WA[1]WA[0]RD[3]RD[2]RD[1]RD[0]
1010$AFormat Control Standard/Enhanced LR/WFA[2]FA[1]FA[0]FD[3]FD[2]FD[1]FD[0]
1011$BRead Register Data Standard/Enhanced L 0 0 0 0 RA[3]RA[2]RA[1]RA[0]
1100$CDisable Self-Test Standard/Enhanced L/S⎯⎯⎯⎯⎯⎯⎯⎯
1101$DActivate Self-Test Standard/Enhanced L/S⎯⎯⎯⎯⎯⎯⎯⎯
1110$ENot Implemented Not Implemented Not Implemented
1111$FReverse Initialization Not Implemented Not Implemented
Sensors
30 NXP Semiconductors
MMA16xx
4.2.1.1 Initialization Command
The initialization command conforms to the description provided in Section 6.1.1 of the DSI Bus Standard V2.5. The
initialization command is only supported as a standard long command. No other commands are recognized by the device until a
valid standard long initialization command is received.
Figure 23 illustrates the sequence of operations performed following negation of internal power-on reset (POR) and execution
of a DSI Initialization command. The BUSOUT node is tested for a bus short to high voltage condition, and the bus fault (BF) flag
is set if an error condition is detected. If no bus fault condition is detected and the BS bit is set in the Initialization command
message, the bus switch will be closed. The device implements a blanking time (t
DSI_BLANK_INIT
) to allow for the bus voltage to
recover following closure of the bus switch.
If the device has been preprogrammed, PA[3:0] and A[3:0] must match the preprogrammed address.
If no device address has been previously programmed into the OTP array, PA[3:0] contains the device address, and A[3:0]
must be zero. If either addressing condition is not met, the device address is not assigned, the bus switch will remain open and
the device will not respond to the Initialization command. If the addressing conditions are met, the new device address is
assigned to A[3:0]. Once the device address is assigned, the new address (A[3:0]) is not protected by the user programmable
OTP array error detection. The user programmable OTP array error detection is calculated and verified using the OTP
programmed values of A[3:0] = ‘0000’.
Once initialized, the device will no longer recognize or respond to Initialization commands.
Table 13. Initialization Command
Data Address Command
CRC
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] C[3] C[2] C[1] C[0]
NV
BS
Bnk[1] Bnk[0] PA[3] PA[2] PA[1] PA[0] A[3] A[2] A[1] A[0] 0 0 0 0 4 bits
Table 14. Initialization Command Bit Definitions
Bit Field Definition
C[3:0] Initialization Command = ‘0000’
A[3:0]
DSI device address. This address is set to the preprogrammed device address following reset, or to ‘0000’ if no preprogrammed address
has been assigned.
PA[3:0] DSI Address to be programmed.
Bnk[1:0]
These bits select the bank address for the user writable data registers. Bank selection affects the Read/Write NVM command operation.
Invalid combinations of B1 and B0 result in no response from the device to the associated initialization. Refer to Section 4.2.1.10 for fur-
ther details regarding register programming and bank selection.
BS
Bus Switch state. This bit controls the state of the DSI bus switch.
1 - Close the bus switch.
0 - Do not close the bus switch.
NV
NVM Program Enable. This bit enables programming of the user-programmed OTP locations. Data to be programmed is transferred to the
device during subsequent Read Write NVM commands.
1 - Enable OTP programming
0 - Disable OTP programming
Table 15. Initialization Command Response
Response
CRC
D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
PA[3] PA[2] PA[1] PA[0] 0 0 0 BF NV
BS
Bnk[1] Bnk[0] PA[3] PA[2] PA[1] PA[0] 4 bits
Table 16. Initialization Response Bit Definitions
Bit Field Definition
PA[3:0]
DSI device address. This field contains the device address. If the device is unprogrammed when the initialization command is issued, the
device address is assigned. This field contains the programmed address. An Initialization command which attempts to assign a device
address of zero is ignored.
Bnk[1:0]
These bits select the bank address for the user writable data registers. Bank selection affects the Read/Write NVM command operation.
Invalid combinations of B1 and B0 result in no response from the device to the associated initialization. Refer to Section 4.2.1.10 for fur-
ther details regarding register programming and bank selection.
BS
Bus Switch state. This bit controls the state of the bus switch:
1 - Close the bus switch
0 - Do not close the bus switch
NV
NVM Program Enable. This bit indicates if programming of the user-accessible OTP is enabled.
1 - OTP programming Enabled
0 - OTP programming Disabled
BF
This bit indicates the success or failure of the bus test performed as part of the Initialization command.
1 - Bus fault detected
0 - Bus test passed

MMA1618KGCWR2

Mfr. #:
Manufacturer:
NXP / Freescale
Description:
Accelerometers DSI2.5 Accelerometer, QFN 16
Lifecycle:
New from this manufacturer.
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