Sensors
NXP Semiconductors 31
MMA16xx
Figure 23. Initialization Sequence
INITIALIZATION
COMMAND?
ENABLE I
RESP
CURRENT
BS == 1?
WAIT FOR NEXT DSI
BUS COMMAND
Y
N
Y
N
Delay t
BUSOUT_DISCHARGE
MEASURE V
BUSOUT
Y
N
V
BUSOUT
< V
THH
?
SET BF FLAG
CLOSE BUS SWITCH
DELAY
Sensors
32 NXP Semiconductors
MMA16xx
4.2.1.2 Request Status Command
The Request Status command is supported in the following command formats:
Standard Long Command
Standard Short Command
Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11)
The device ignores the Request Status command if the DSI device address is set to the DSI Global Device Address of ‘0000’.
The data bits D[7:0] in the command are only used in the CRC calculation.
Table 17. Request Status Command
Data Address Command
CRC
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] C[3] C[2] C[1] C[0]
A[3] A[2] A[1] A[0] 0 0 0 1 0 to 8 bits
Table 18. Request Status Command Bit Definitions
Bit Field Definition
C[3:0] Request Status Command = ‘0001’
A[3:0]
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
D[7:0] Used for CRC calculation only
Table 19. Short Response - Request Status Command
Response
CRC
D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0 0 0 0 0 0 0NVUST
BS
AT[1] AT[0] S 0 0 to 8 bits
Table 20. Long Response - Request Status Command
Data
CRC
D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
A[3]A[2]A[1]A[0]0000NVUST
BS
AT[1] AT[0] S 0 0 to 8 bits
Table 21. Request Status Response Bit Definitions
Bit Field Definition
S
This bit indicates whether the device has detected an internal device error.
1 - Internal Error detected.
0 - No Internal Error detected
Reference Table 60 for conditions that set the S bit.
AT[1:0] Attribute bits located in Register DEVCFG1 (Reference Section 3.1.4.1)
BS
Bus Switch state. This bit controls the state of the bus switch:
1 - Close the bus switch
0 - Do not close the bus switch
ST
This bit indicates whether internal self-test circuitry is active
1 - Self-Test active
0 - Self-Test disabled
U This bit is set if the voltage at HCAP is below the threshold specified in Section 2. Refer to Section 3.3.2 for details.
NV
NVM Program Enable. This bit indicates whether programming of the user-programmable OTP locations is enabled.
1 - OTP programming Enabled
0 - OTP programming Disabled
A[3:0] DSI device address. This field contains the device address.
Shaded bits are transmitted to meet the response message length of the received message
Sensors
NXP Semiconductors 33
MMA16xx
4.2.1.3 Read Acceleration Data Command
The Read Acceleration Data command is supported in the following command formats:
Standard Long Command
Standard Short Command
Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
Enhanced Short Command as configured by the Form at Control Command (Reference Section 4.2.1.11)
The device ignores the Request Status command if the DSI device address is set to the DSI Global Device Address of ‘0000’.
The data bits D[7:0] in the command are only used in the CRC calculation.
The device truncates the LSBs for Acceleration Data Responses of length less than 10. If the result of the truncation is 0, the
minimum acceleration value is transmitted as defined in Table 27.
Table 22. Read Acceleration Data Command
Data Address Command
CRC
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] C[3] C[2] C[1] C[0]
A[3] A[2] A[1] A[0] 0 0 1 0 0 to 8 bits
Table 23. Read Acceleration Data Command Bit Definitions
Bit Field Definition
C[3:0] Read Acceleration Data Command = ‘0010’
A[3:0]
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
D[7:0] Used for CRC calculation only
Table 24. Short Response - Read Acceleration Data Command
Response
Length
Response
CRC
D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
8 AD[9] AD[8] AD[7] AD[6] AD[5] AD[4] AD[3] AD[2]
0 to 8 bits
9 AD[9] AD[8] AD[7] AD[6] AD[5] AD[4] AD[3] AD[2] AD[1]
10
AD[9] AD[8] AD[7] AD[6] AD[5] AD[4] AD[3] AD[2] AD[1] AD[0]
11
S
12
0
13
ST14
AT_OTP[0]
15
AT_OTP[1]
Table 25. Long Response - Read Acceleration Data Command
Response
CRC
D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
A[3] A[2] A[1] A[0] 0 S AD[9] AD[8] AD[7] AD[6] AD[5] AD[4] AD[3] AD[2] AD[1] AD[0] 0 to 8 bits
Table 26. Read Acceleration Response Bit Definitions
Bit Field Definition
AD[9:0] Ten-bit acceleration result produced by the device.
S
This bit indicates whether the device has detected an internal device error.
1 - Internal Error detected.
0 - No Internal Error detected
Reference Table 60 for conditions that set the S bit.
ST
This bit indicates whether internal self-test circuitry is active
1 - Self-Test active
0 - Self-Test disabled
A[3:0] DSI device address. This field contains the device address.
AT_OTP[1:0] Attribute bits located in Register DEVCFG1 (Reference Section 3.1.4.1)
Shaded bits are transmitted to meet the response message length of the received message

MMA1618KGCWR2

Mfr. #:
Manufacturer:
NXP / Freescale
Description:
Accelerometers DSI2.5 Accelerometer, QFN 16
Lifecycle:
New from this manufacturer.
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