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NB3H83905CDTR2G

P1-P3P4-P6P7-P9P10-P12P13-P14
NB3H83905C
http://onsemi.com
10
Figure 6. Typical Phase Noise Plot of the NB3H83905C Operating at 25 MHz V
DD
= V
DDO
= 2.5 V
BCLKx IN
Z
O
= 50 W
NB3H83905C
Scope
50 W
V
DD
V
DDO
DUT
GND
Figure 7. Typical Device Evaluation and Termination Setup − See Table 8
GND
Table 8. TEST SUPPLY SETUP. V
DDO
SUPPLY MAY BE CENTERED ON 0.0 V (SCOPE GND) TO PERMIT DIRECT
CONNECTION INTO “50 W TO GND” SCOPE MODULE. V
DD
SUPPLY TRACKS DUT GND PIN
Spec Condition: Test Setup V
DD
: Test Setup V
DDO
: Test Setup DUT GND:
V
DD
= V
DDO
= 3.135 V to 3.465 V (3.3 V $5%) 1.56 to 1.73 V 1.56 to 1.73 V −1.56 to −1.73 V
V
DD
= V
DDO
= 2.375 V to 2.625 V (2.5 V $5%) 1.1875 to 1.3125 V 1.1875 to 1.3125 V −1.1875 to −1.3125 V
V
DD
= V
DDO
= 1.6 V to 2.0 V (1.8 V $0.2 V) 0.8 to 1.0 V 0.8 to 1.0 V −0.8 to −1.0 V
V
DD
= 3.135 V to 3.465 V (3.3 V $5%);
V
DDO
= 2.375 V to 2.625 V (2.5 V $5%)
1.955 to 2.1525 V 1.1875 to 1.3125 V −1.1875 to −1.3125 V
V
DD
= 3.135 V to 3.465 V (3.3 V $5%);
V
DDO
= 1.6 V to 2.0 V (1.8 V $0.2 V)
2.335 to 2.465 V 0.8 to 1.0 V −0.8 to −1.0 V
V
DD
= 2.375 V to 2.625 V (2.5 V $5%);
V
DDO
= 1.6 V to 2.0 V (1.8 V $0.2 V)
1.575 to 1.625 V 0.8 to 1.0 V −0.8 to −1.0 V
NB3H83905C
http://onsemi.com
11
APPLICATION INFORMATION
Crystal Input Interface
Figure 8 shows the NB3H83905C device crystal
oscillator interface using a typical parallel resonant crystal.
A parallel crystal with loading capacitance C
L
= 18 pF
would use C1 = 32 pF and C2 = 32 pF as nominal values,
assuming 4 pF of stray cap per line. The frequency accuracy
and duty cycle skew can be fine tuned by adjusting the C1
and C2 values. For example, increasing the C1 and C2
values will reduce the operational frequency. Note R1 is
optional and may be 0 W.
Figure 8. NB3H83905C Crystal Oscillator Interface
* R1 is optional
32 pF
32 pF
C1
C2
NB3H83905C
XTAL_IN/CLK
XTAL_OUT
R1*
X1 18 pF
Parallel Resonant
Crystal
Termination
NB3H83905C device output series termination may be
used by locating a 28 W series resistor at the driver pin as
shown in Figure 9. Alternatively, a Thevenin Parallel
termination may be used by locating a 100 W pullup resistor
to V
DD
and a 100 W pullup resistor to GND at the receiver
pin, instead of an Rs source termination resistor, Figure 10.
Unused Input and Output Pins
All LVCMOS control pins have internal pull−ups or
pull−downs; additional external resistors are not required
(optionally 1 kW resistors may be used). All unused
LVCMOS outputs can be left floating with no trace attached.
Bypass
The V
DD
and V
DDO
supply pins should be bypassed with
both a 10 mF and a 0.1 mF cap from supply pins to GND.
Figure 9. Series Termination
Figure 10. Optional Thevenin Termination
Rseries = 28 W
BCLKx
LVCMOS
R = 100 W
R = 100 W
LVCMOS
BCLKx
ORDERING INFORMATION
Device Package Shipping
†
NB3H83905CDG SOIC−16
(Pb*Free)
48 Units / Rail
NB3H83905CDR2G SOIC−16
(Pb*Free)
2500 Units / Tape & Reel
NB3H83905CDTG TSSOP−16
(Pb*Free)
96 Units /Rail
NB3H83905CDTR2G TSSOP−16
(Pb*Free)
2500 Units / Tape & Reel
NB3H83905CMNG QFN−20
(Pb−Free)
92 Units / Rail
NB3H83905CMNTXG QFN−20
Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NB3H83905C
http://onsemi.com
12
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B
S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A
S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
____
6.40
16X
0.58
16X
1.12
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
16
89
8X
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
P1-P3P4-P6P7-P9P10-P12P13-P14

NB3H83905CDTR2G

Mfr. #:
Buy NB3H83905CDTR2G
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 1.8V/2.5V/3.3 V BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
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