OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

XR21V1414IM48-F

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34
XR21V1414
22
4-CH FULL-SPEED USB UART
REV. 1.3.0
T
ABLE
9: TX
AND
RX C
LOCK
M
ASK
V
ALUES
I
NDEX
(D
ECIMAL
)
TX C
LOCK
M
ASK
(H
EX
)
RX C
LOCK
M
ASK
(H
EX
) -
E
VEN
C
LOCK
D
IVISOR
RX C
LOCK
M
ASK
(H
EX
) -
O
DD
C
LOCK
D
IVISOR
0 0x0000 0x0000 0x0000
1 0x0000 0x0000 0x0000
2 0x0100 0x0000 0x0100
3 0x0020 0x0400 0x0020
4 0x0010 0x0100 0x0010
5 0x0208 0x0040 0x0208
6 0x0104 0x0820 0x0108
7 0x0844 0x0210 0x0884
8 0x0444 0x0110 0x0444
9 0x0122 0x0888 0x0224
10 0x0912 0x0448 0x0924
11 0x0492 0x0248 0x0492
12 0x0252 0x0928 0x0292
13 0x094A 0x04A4 0x0A52
14 0x052A 0x0AA4 0x054A
15 0x0AAA 0x0954 0x04AA
16 0x0AAA 0x0554 0x0AAA
17 0x0555 0x0AD4 0x05AA
18 0x0B55 0x0AB4 0x055A
19 0x06B5 0x05AC 0x0B56
20 0x05B5 0x0D6C 0x06D6
21 0x0B6D 0x0B6A 0x0DB6
22 0x076D 0x06DA 0x0BB6
23 0x0EDD 0x0DDA 0x076E
24 0x0DDD 0x0BBA 0x0EEE
25 0x07BB 0x0F7A 0x0DDE
26 0x0F7B 0x0EF6 0x07DE
27 0x0DF7 0x0BF6 0x0F7E
28 0x07F7 0x0FEE 0x0EFE
29 0x0FDF 0x0FBE 0x07FE
30 0x0F7F 0x0EFE 0x0FFE
31 0x0FFF 0x0FFE 0x0FFD
XR21V1414
23
REV. 1.3.0
4-CH FULL-SPEED USB UART
3.3.5 CHARACTER_FORMAT Register Description (Read/Write)
This register controls the character format such as the word length (7, 8 or 9), parity (odd, even, forced ’0’, or
forced ’1’) and number of stop bits (1 or 2).
CHARACTER_FORMAT[3:0]: Data Bits.
All other values for CHARACTER_FORMAT[3:0] are reserved.
CHARACTER_FORMAT[6:4]: Parity Mode Select
These bits select the parity mode. If 9-bit data mode has been selected, then writing to these bits will not have
any effect. In other words, there will not be an additional parity bit.
CHARACTER_FORMAT[7]: Stop Bit select
This register selects the number of stop bits to add to the transmitted character and how many stop bits to
check for in the received character.
3.3.6 FLOW_CONTROL Register Description (Read/Write)
These registers select the flow control mode. These registers should only be written to when the UART is
disabled. Writing to the FLOW_CONTROL register when the UART is enabled will result in undefined
behavior. Note that the FLOW_CONTROL register settings are used in conjunction with the GPIO_MODE
register.
T
ABLE
10: D
ATA
B
ITS
D
ATA
B
ITS
CHARACTER_FORMAT[3:0]
7 0111
8 1000
9 1001
T
ABLE
11: P
ARITY
S
ELECTION
B
IT
-6 B
IT
-5 B
IT
-4 P
ARITY SELECTION
0 0 0 No parity
0 0 1 Odd parity
0 1 0 Even parity
0 1 1 Force parity to mark, “1”
1 0 0 Force parity to space, “0”
T
ABLE
12: S
TOP
B
IT
S
ELECTION
B
IT
-7 N
UMBER OF
S
TOP
B
ITS
0 1 stop bit
2 2 stop bits
XR21V1414
24
4-CH FULL-SPEED USB UART
REV. 1.3.0
FLOW_CONTROL[2:0]: Flow control mode select
FLOW_CONTROL[3]: Half-Duplex Mode
•
Logic 0 = Normal (full-duplex) mode. The UART can transmit and receive data at the same time.
•
Logic 1 = Half-duplex Mode. In half-duplex mode, any data on the RX pin is ignored when the UART is
transmitting data.
FLOW_CONTROL[7:4]: Reserved
These bits are reserved and should remain ’0’.
3.3.7 XON_CHAR, XOFF_CHAR Register Descriptions (Read/Write)
The XON_CHAR and XOFF_CHAR registers store the XON and XOFF characters, respectively, that are used
in the Automatic Software Flow control.
XON_CHAR[7:0]: XON Character
In Automatic Software Flow control mode, the UART will resume data transmission when the XON character
has been received.
For behavior in the Address Match mode, see “Section 1.5.9, Multidrop Mode with address matching” on
page 14.
For behavior in the Address Match with TX Flow Control mode, see “Section 1.5.9, Multidrop Mode with
address matching” on page 14.
XOFF_CHAR[7:0]: XOFF Character
In Automatic Software Flow control mode, the UART will suspend data transmission when the XOFF character
has been received.
For behavior in the Address Match mode, see “Section 1.5.9, Multidrop Mode with address matching” on
page 14.
For behavior in the Address Match with TX Flow Control mode, see “Section 1.5.10, Programmable Turn-
Around Delay” on page 14.
T
ABLE
13: F
LOW
C
ONTROL
M
ODE
S
ELECTION
M
ODE
B
IT
-2 B
IT
-1 B
IT
-0 M
ODE
D
ESCRIPTION
0 0 0 0 No flow control, no address matching.
1 0 0 1 HW flow control enabled. Auto RTS/CTS or DTR/DSR must be selected by
GPIO_MODE.
2 0 1 0 SW flow control enabled
3 0 1 1 Multidrop mode - RX only after address match, TX independent. (Typically
used with GPIO_MODE 3)
4 1 0 0 Multidrop mode - RX / TX only after address match. (Typically used with
GPIO_MODE 4)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34

XR21V1414IM48-F

Mfr. #:
Buy XR21V1414IM48-F
Manufacturer:
MaxLinear
Description:
USB Interface IC 4-Ch 12Mbps 48MHz Internal clock; UART
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet