XR21V1414
28
4-CH FULL-SPEED USB UART
REV. 1.3.0
3.4.1 CUSTOM Register Description (Read/Write)
This register enables the Wide mode functionality for the UART.
CUSTOM[0]: Enable wide mode
•
Logic 0 = Normal (7, 8 or 9 bit data) mode
•
Logic 1 = Wide mode - See “Section 1.5.1.1, Wide Mode Transmit” on page 11, “Section 1.5.2.3, Wide
mode receive operation with 7 or 8-bit data” on page 12 and “Section 1.5.2.4, Wide mode receive
operation with 9-bit data” on page 12.
CUSTOM[1]: Max Packet Size
•
Logic 0 = bMaxPacketSize = 64 bytes
Logic 1 = bMaxPacketSize = 63 bytes (this bit is automatically set to ’1’ if the XR21V1414 receives a
CDC_ACM USB command)
CUSTOM[7:2]: Reserved
These bits are reserved and should remain ’0’.
3.4.2 LOW_LATENCY Register Description (Read/Write)
This register is automatically set to logic ’1’ for baud rates below 46921 bps, and can be manually set for baud
rates of 46921 bps and higher. This register enables the Low latency feature of the UART. Write to this
register following any desired baud rate setting change.
LOW_LATENCY[0]: Enable Low Latency mode
•
Logic 0 = Receive data is not forwarded from the Rx FIFO until bMaxPacketSize (64 bytes) or timeout (3
characters) has occurred.
•
Logic 1 = All data in the RX FIFO is provided to the USB host at the next BULK IN request irrespective of the
number of bytes in the FIFO.
LOW_LATENCY[7:1]: Reserved
These bits are reserved and should remain ’0’.
3.4.3 CUSTOM_INT_PACKET (Read/Write)
This register is used to enable / disable GPIO status in the high data byte of the custom interrupt packet. See
Table 16, “Interrupt Packet Format,” on page 29 and Table 18, “Data Field of Customized Interrupt
Packet - Exar Vendor Specific,” on page 30.
CUSTOM_INT_PACKET[0]: GPIO1
•
Logic 0 = Disable GPIO1 status in custom interrupt packet.
•
Logic 1 = Enable GPIO1 status in custom interrupt packet.
