Philips
Semiconductors
GTL2000
22-bit bi-directional low voltage translator
Product data
Supersedes data of 2000 Jan 25
2003 Apr 01
INTEGRATED CIRCUITS
Philips Semiconductors Product data
GTL200022-bit bi-directional low voltage translator
2
2003 Apr 01
FEATURES
22-bit bi-directional low voltage translator
Allows voltage level translation between 1.0 V, 1.2 V, 1.5 V, 1.8 V,
2.5 V, 3.3 V, and 5 V busses which allows direct interface with
GTL, GTL+, LVTTL/TTL and 5 V CMOS levels
Provides bi-directional voltage translation with no direction pin
Low 6.5 RDS
ON
resistance between input and output pins
(Sn/Dn)
Supports hot insertion
No power supply required - Will not latch up
5 V tolerant inputs
Low stand-by current
Flow-through pinout for ease of printed circuit board trace routing
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V
MM per JESD22-A115, and 1000 V per JESD22-C101
Package offer: SSOP48, TSSOP48
APPLICATIONS
Any application that requires bi-directional or unidirectional
voltage level translation from any voltage between 1.0 V & 5.0 V
to any voltage between 1.0 V & 5.0 V
The open drain construction with no direction pin is ideal for
bi-directional low voltage (e.g., 1.0 V, 1.2 V, 1.5 V, or 1.8 V)
processor I
2
C port translation to the normal 3.3 V and/or 5.0 V I
2
C
bus signal levels or GTL/GTL+ translation to LVTTL/TTL signal
levels.
DESCRIPTION
The Gunning Transceiver Logic — Transceiver Voltage Clamps
(GTL-TVC) provide high-speed voltage translation with low
ON-state resistance and minimal propagation delay. The GTL2000
provides 22 NMOS pass transistors (Sn and Dn) with a common
gate (G
REF
) and a reference transistor (S
REF
and D
REF
). The device
allows bi-directional voltage translations between 1.0 V and 5.0 V
without use of a direction pin.
When the Sn or Dn port is low the clamp is in the ON-state and a
low resistance connection exists between the Sn and Dn ports.
Assuming the higher voltage is on the Dn port, when the Dn port is
high, the voltage on the Sn port is limited to the voltage set by the
reference transistor (S
REF
). When the Sn port is high, the Dn port is
pulled to V
CC
by the pull up resistors. This functionality allows a
seamless translation between higher and lower voltages selected by
the user, without the need for directional control.
All transistors have the same electrical characteristics and there is
minimal deviation from one output to another in voltage or
propagation delay. This is a benefit over discrete transistor voltage
translation solutions, since the fabrication of the transistors is
symmetrical. Because all transistors in the device are identical,
S
REF
and D
REF
can be located on any of the other twenty-two
matched Sn/Dn transistors, allowing for easier board layout. The
translator’s transistors provides excellent ESD protection to lower
voltage devices and at the same time protect less ESD resistant
devices.
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE ORDER CODE TOPSIDE MARK DWG NUMBER
48-Pin Plastic SSOP -40 to +85 °C GTL2000DL GTL2000DL SOT370-1
48-Pin Plastic TSSOP -40 to +85 °C GTL2000DGG GTL2000DGG SOT362-1
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
Philips Semiconductors Product data
GTL2000
22-bit bi-directional low voltage translator
2003 Apr 01
3
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
21
22
23
24
41
42
43
44
45
46
47
48
S
REF
S
1
S
2
S
3
S
4
S
5
S
6
S
7
S
8
S
9
S
10
S
11
S
12
S
13
S
14
S
15
S
16
S
17
S
18
S
19
S
20
S
21
S
22
G
REF
D
REF
GND
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
D
11
D
12
D
13
D
14
D
15
D
16
D
17
D
18
D
19
D
20
D
21
D
22
SA00521
PIN DESCRIPTION
PIN
NUMBER
SYMBOL NAME AND FUNCTION
1 GND Ground (0 V)
2 S
REF
Source of reference transistor
3 - 24 S
n
Port S
1
to Port S
22
25 - 46 D
n
Port D
1
to Port D
22
47 D
REF
Drain of reference transistor
48 G
REF
Gate of reference transistor
FUNCTION TABLE
HIGH to LOW translation assuming Dn is at the higher voltage level
GREF
DREF SREF In-Dn Out-Sn Transistor
H H 0 V X X Off
H H V
TT
H V
TT
1
On
H H V
TT
L L
2
On
L L 0 - V
TT
X X Off
H = High voltage level
L = Low voltage level
X = Dont Care
NOTES:
1. Sn is not pulled up or pulled down.
2. Sn follows the Dn input low.
3. G
REF
should be at least 1.5 V higher than S
REF
for best
translator operation.
4. V
TT
is equal to the S
REF
voltage.
FUNCTION TABLE
LOW to HIGH translation assuming Dn is at the higher voltage level
GREF DREF SREF In-Sn Out-Dn Transistor
H H 0 V X X Off
H H V
TT
V
TT
H
1
nearly off
H H V
TT
L L
2
On
L L 0 - V
TT
X X Off
H = High voltage level
L = Low voltage level
X = Dont Care
NOTES:
1. Dn is pulled up to V
CC
through an external resistor.
2. Dn follows the Sn input low.
3. G
REF
should be at least 1.5 V higher than S
REF
for best
translator operation.
4. V
TT
is equal to the S
REF
voltage.
CLAMP SCHEMATIC
SA00522
S
REF
S
1
S
22
D
REF
D
1
D
22
G
REF

GTL2000DL,518

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC TRNSLTR BIDIRECTIONAL 48SSOP
Lifecycle:
New from this manufacturer.
Delivery:
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