ADM1023
Rev. 8 | Page 13 of 18 | www.onsemi.com
1. The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line, SDATA, while the serial clock line, SCLK, remains
high. This indicates that an address/data stream will follow.
All slave peripherals connected to the serial bus respond to
the start condition and shift in the next 8 bits. These bits
consist of a 7-bit address (MSB first) plus an R/
W
bit, which
determines the direction of the data transfer, that is, whether
data is written to, or read from, the slave device.
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the Acknowl-
edge bit. All other devices on the bus remain idle while the
selected device waits for data to be read from or written to it.
If the R/
W
bit is 0, the master writes to the slave device. If the
R/
W
bit is 1, the master reads from the slave device.
2. Data is sent over the serial bus in sequences of nine clock
pulses, 8 bits of data followed by an Acknowledge bit from
the slave device. Transitions on the data line must occur
during the low period of the clock signal and remain stable
during the high period, because a low-to-high transition
when the clock is high may be interpreted as a stop signal.
The number of data bytes that can be transmitted over the
serial bus in a single read or write operation is limited only
by what the master and slave devices can handle.
3. When all data bytes have been read or written, stop condi-
tions are established. In write mode, the master pulls the
data line high during the 10th clock pulse to assert a stop
condition. In read mode, the master device overrides the
Acknowledge bit by pulling the data line high during the
low period before the ninth clock pulse. This is known as
No Acknowledge. The master then takes the data line low
during the low period before the 10th clock pulse, then high
during the 10th clock pulse to assert a stop condition.
R/W
0
SCLK
SDAT
A
1011A1A0 D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADM1023
START BY
MASTER
191
ACK. BY
ADM1023
9
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADM1023
STOP BY
MASTER
1
9
SCLK (CONTINUED)
SDATA (CONTINUED)
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
FRAME 3
DATA BYTE
00058-016
Figure 16. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
0
SCLK
SDAT
A
1 0 1 1 A1 A0 D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADM1023
START BY
MASTER
19
1
ACK. BY
ADM1023
9
STOP BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
00058-017
R/W
Figure 17. Writing to the Address Pointer Register Only
SCLK
SDATA
D7
D6
D5
D4
D3
D2
D1
D0
NO ACK.
BY MASTER
START BY
MASTER
91
ACK. BY
ADM1023
9
STOP BY
MASTER
A6
A5
A4
A3
A2
A1 A0
1
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
DATA BYTE FROM ADM1023
00058-018
R/W
Figure 18. Reading Data from a Previously Selected Register
ADM1023
Rev. 8 | Page 14 of 18 | www.onsemi.com
Any number of bytes of data may be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation because the type of operation is determined
at the beginning and cannot subsequently be changed without
starting a new operation.
For the ADM1023, write operations contain either one or two
bytes, while read operations contain one byte and perform the
following functions:
To write data to one of the device data registers or read data
from it, the address pointer register must be set so that the
correct data register is addressed. Data can then be written into
that register or read from it. The first byte of a write operation
always contains a valid address that is stored in the address
pointer register. If data is to be written to the device, the write
operation contains a second data byte that is written to the
register selected by the address pointer register.
This is illustrated in Figure 16. The device address is sent over
the bus followed by R/
W
set to 0. This is followed by two data
bytes. The first data byte is the address of the internal data
register to be written to, which is stored in the address pointer
register. The second data byte is the data to be written to the
internal data register.
When reading data from a register, there are two possibilities:
1. If the ADM1023’s address pointer register value is unknown
or not the desired value, it is necessary to set it to the correct
value before data can be read from the desired data register.
This is done by performing a write to the ADM1023 as
before, but only the data byte containing the register read
address is sent, as data is not to be written to the register.
This is shown in Figure 17.
A read operation is then performed consisting of the serial
bus address, R/
W
bit set to 1, followed by the data byte read
from the data register. This is shown in Figure 18.
2. If the address pointer register is known to be at the desired
address already, data can be read from the corresponding
data register without first writing to the address pointer
register.
NOTES
It is possible to read a data byte from a data register with-
out first writing to the address pointer register. However,
it is not possible to write data to a register without writing
to the address pointer register even if the address pointer
register is already at the correct value. This is because the
first data byte of a write is always written to the address
pointer register.
Do not forget that ADM1023 registers have different
addresses for read and write operations. The write address
of a register must be written to the address pointer if data
is to be written to that register, but it is not possible to read
data from that address. The read address of a register must
be written to the address pointer before data can be read
from that register.
ALERT
OUTPUT
The
ALERT
output goes low whenever an out-of-limit measure-
ment is detected or if the remote temperature sensor is open-
circuit. It is an open drain and requires a 10 kΩ pull-up to V
DD
.
Several
ALERT
outputs can be wire-ANDed together, so that
the common line goes low if one or more of the
ALERT
outputs
goes low.
The
ALERT
output can be used as an interrupt signal to a
processor, or it may be used as an
SMBALERT
. Slave devices
on the SMBus normally cannot signal to the master that they
want to talk, but the
SMBALERT
function allows them to do so.
One or more
ALERT
outputs are connected to a common
SMBALERT
line connected to the master. When the
SMBALERT
line is pulled low by one of the devices, the
procedure shown in Figure 19 occurs.
00058-019
MASTER
RECEIVES
SMBALERT
MASTER SENDS
ARA AND READ
COMMAND
DEVICE SENDS
ITS ADDRESS
NO
ACK
START
ALERT RESPONSE
ADDRESS
RD ACK
DEVICE
ADDRESS
STOP
Figure 19. Use of SMBALERT
ADM1023
Rev. 8 | Page 15 of 18 | www.onsemi.com
SMBALERT Process
1.
SMBALERT
pulled low.
2. Master initiates a read operation and sends the alert response
address (ARA = 0001 100). This is a general call address that
must not be used as a specific device address.
3. The device whose
ALERT
output is low responds
to the ARA and the master reads its device address.
The address of the device is now known, and it can
be interrogated in the usual way.
4. If more than one devices
ALERT
output is low, the one
with the lowest device address has priority, in accordance
with normal SMBus arbitration.
5. Once the ADM1023 has responded to the ARA, it resets its
ALERT
output, provided that the error condition that caused
the
ALERT
no longer exists. If the
SMBALERT
line remains
low, the master sends ARA again, and so on until all devices
whose
ALERT
outputs were low have responded.
LOW POWER STANDBY MODES
The ADM1023 can be put into a low power standby mode using
hardware or software, that is, by taking the
STBY
input low or
by setting Bit 6 of the configuration register. When
STBY
is
high or Bit 6 is low, the ADM1023 operates normally. When
STBY
is pulled low or Bit 6 is high, the ADC is inhibited, and
any conversion in progress is terminated without writing the
result to the corresponding value register.
The SMBus is still enabled. Power consumption in the standby
mode is reduced to less than 10 μA if there is no SMBus activity,
or 100 μA if there are clock and data signals on the bus.
These two modes are similar but not identical. When
STBY
is
low, conversions are completely inhibited. When Bit 6 is set,
but
STBY
is high, a one-shot conversion of both channels can
be initiated by writing any data value to the one-shot register
(Address 0x0F).
SENSOR FAULT DETECTION
The ADM1023 has a fault detector at the D+ input that detects
if the external sensor diode is open-circuit. This is a simple
voltage comparator that trips if the voltage at D+ exceeds
V
CC
− 1 V (typical). The output of this comparator is checked
when a conversion is initiated and sets Bit 2 of the status
register if a fault is detected.
If the remote sensor voltage falls below the normal measuring
range, for example, due to the diode being short-circuited,
the ADC outputs –128°C (1000 0000 000). Because the normal
operating temperature range of the device extends only down
to 0°C, this output code is never seen in normal operation and
can be interpreted as a fault condition.
In this respect, the ADM1023 differs from, and improves upon,
competitive devices that output 0 if the external sensor goes
short-circuit. Unlike the ADM1023, these other devices can
misinterpret a genuine 0°C measurement as a fault condition.
If the external diode channel is not being used and is shorted
out, the resulting
ALERT
may be cleared by writing 0x80
(−128°C) to the low limit register.

EVAL-ADM1023EB

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
BOARD EVAL FOR ADM1023
Lifecycle:
New from this manufacturer.
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