ICS854S01AKI REVISION A OCTOBER 29, 2012 2 ©2012 Integrated Device Technology, Inc.
ICS854S01I Data Sheet 2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Function Tables
Table 3. Control Input Function Table
Number Name Type Description
1 PCLK0 Input Pulldown Non-inverting differential clock input.
2 nPCLK0 Input
Pullup/
Pulldown
Inverting differential clock input. V
DD
/2 default when left floating.
3 PCLK1 Input Pulldown Non-inverting differential clock input.
4 nPCLK1 Input
Pullup/
Pulldown
Inverting differential clock input. V
DD
/2 default when left floating.
5 RESERVED Reserve Reserve pin.
6 CLK_SEL Input Pulldown
Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When
LOW, selects PCLK0, nPCLK0 inputs. LVCMOS / LVTTL interface levels.
7, 16 nc Unused No connects.
8, 13 V
DD
Power Power supply pins.
9, 12, 14, 15 GND Power Power supply ground.
10, 11 nQ, Q Output Differential output pair. LVDS interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 2 pF
R
PULLUP
Input Pullup Resistor 37 k
R
PULLDOWN
Input Pulldown Resistor 37 k
CLK_SEL PCLK Selected
0 PCLK0, nPCLK0
1 PCLK1, nPCLK1
