854S01AKILF Datasheet 854S01AKILF | P4-P6

ICS854S01I Data Sheet 2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER

Table 4D. LVDS DC Characteristics, V

= 3.3V ± 5%, T

= -40°C to 85°C

AC Electrical Characteristics

Table 5. AC Characteristics, V

= 3.3V ± 5%, T

= -40°C to 85°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE: All parameters measured at  1.0GHz unless otherwise noted.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and

with equal load conditions. Using the same type of inputs on each device, the outputs are measured

at the differential cross points.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 4: Q, nQ outputs measured differentially. See Parameter Measurement Information to MUX Isolation diagram.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

Differential Output Voltage 247 454 mV

V

Magnitude Change 50 mV

Offset Voltage 1.125 1.375 V

V

Magnitude Change 50 mV

Symbol Parameter Test Conditions Minimum Typical Maximum Units

OUT

Output Frequency 2.5 GHz

Propagation Delay;

NOTE 1

250 400 600 ps

tjit

Buffer Additive Phase Jitter,

RMS; refer to Additive Phase

Jitter Section

155.52MHz, Integration Range:

12kHz – 20MHz)

0.06 ps

tsk(pp)

Part-to-Part Skew;

NOTE 2, 3

350 ps

/ t

Output Rise/Fall Time 20% to 80% 100 275 ps

odc Output Duty Cycle 49 51 %

MUX_

ISOLATION

MUX Isolation;

NOTE 4

OUT

= 155.52MHz, V

400mV

86 dB

ICS854S01I Data Sheet 2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER

Additive Phase Jitter

The spectral purity in a band at a specific offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot

and is most often the specified plot in many applications. Phase noise

is defined as the ratio of the noise power present in a 1Hz band at a

specified offset from the fundamental frequency to the power value of

the fundamental. This ratio is expressed in decibels (dBm) or a ratio

of the power in the 1Hz band to the power in the fundamental. When

the required offset is specified, the phase noise is called a dBc value,

which simply means dBm at a specified offset from the fundamental.

By investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the entire

time record of the signal. It is mathematically possible to calculate an

expected bit error rate given a phase noise plot.

As with most timing specifications, phase noise measurements has

issues relating to the limitations of the equipment. Often the noise

floor of the equipment is higher than the noise floor of the device. This

is illustrated above. The device meets the noise floor of what is

shown, but can actually be lower. The phase noise is dependent on

the input source and measurement equipment.

The source generator "IFR2042 10kHz – 56.4GHz Low Noise Signal

Generator as external input to an Agilent 8133A 3GHz Pulse

Generator"

Additive Phase Jitter @ 155.52MHz

12kHz to 20MHz = 0.06ps (typical)

SSB Phase Noise dBc/Hz

Offset from Carrier Frequency (Hz)

ICS854S01I Data Sheet 2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER

Parameter Measurement Information

LVDS Output Load AC Test Circuit

Part-to-Part Skew

Output Rise/Fall Time

Differential Input Level

MUX Isolation

Propagation Delay

SCOPE

3.3V±5%

POWER SUPPLY

+–

Float GND

nQx

nQy

sk(pp)

Part 1

Part 2

20%

80%

20%

nPCLK[0:1]

PCLK[0:1]

GND

CMR

Cross Points

Amplitude (dB)

Spectrum of Output Signal Q

MUX

_ISOL

= A0 – A1

(fundamental)

Frequency

MUX selects static input

MUX selects active

input clock signal

nPCLK[0:1]

PCLK[0:1

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

854S01AKILF

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Description:

Clock Drivers & Distribution 2:1 Diff to LVDS Multplexer 2.5GHz

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