IDT
®
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI 1586P - 11/19/15
9ZX21901B
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
3
Pin Description
PIN # PIN NAME PIN TYPE DESCRIPTION
1 VDDA PWR 3.3V power for the PLL core.
2 GNDA PWR Ground pin for the PLL core.
3 IREF OUT
This pin establishes the reference for the differential current-mode output pairs.
It requires a fixed precision resistor to ground. 475ohm is the standard value
for 100ohm differential impedance. Other impedances require different values.
See data sheet.
4 100M_133M# IN
Input to select operating frequency
1 = 100MHz, 0 = 133.33MHz
5 HIBW_BYPM_LOBW# IN
Trilevel input to select High BW, Bypass or Low BW mode.
See PLL Operating Mode Table for Details.
6 CKPWRGD_PD# IN
Notifies device to sample latched inputs and start up on first high assertion, or
exit Power Down Mode on subsequent assertions. Low enters Power Down
Mode.
7 GND PWR Ground pin.
8VDDR PWR
3.3V power for differential input clock (receiver). This VDD should be treated
as an analog power rail and filtered appropriately.
9 DIF_IN IN 0.7 V Differential TRUE input
10 DIF_IN# IN 0.7 V Differential Complementary Input
11 SMB_A0_tri IN
SMBus address bit. This is a tri-level input that works in conjunction with the
SMB_A1 to decode 1 of 9 SMBus Addresses.
12 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant
13 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant
14 SMB_A1_tri IN
SMBus address bit. This is a tri-level input that works in conjunction with the
SMB_A0 to decode 1 of 9 SMBus Addresses.
15 DFB_IN IN
True half of differential feedback input, provides feedback signal to the PLL for
synchronization with the input clock to elimate phase error.
16 DFB_IN# IN
Complementary half of differential feedback input, provides feedback signal to
the PLL for synchronization with input clock to elimate phase error.
17 DFB_OUT# OUT
Complementary half of differential feedback output, provides feedback signal
to the PLL for synchronization with input clock to eliminate phase error.
18 DFB_OUT OUT
True half of differential feedback output, provides feedback signal to the PLL
for synchronization with the input clock to eliminate phase error.
19 DIF_0 OUT 0.7V differential true clock output
20 DIF_0# OUT 0.7V differential Complementary clock output
21 VDD PWR Power supply, nominal 3.3V
22 DIF_1 OUT 0.7V differential true clock output
23 DIF_1# OUT 0.7V differential Complementary clock output
24 DIF_2 OUT 0.7V differential true clock output
25 DIF_2# OUT 0.7V differential Complementary clock output
26 GND PWR Ground pin.
27 DIF_3 OUT 0.7V differential true clock output
28 DIF_3# OUT 0.7V differential Complementary clock output
29 DIF_4 OUT 0.7V differential true clock output
30 DIF_4# OUT 0.7V differential Complementary clock output
31 VDD PWR Power supply, nominal 3.3V
32 DIF_5 OUT 0.7V differential true clock output
33 DIF_5# OUT 0.7V differential Complementary clock output
34 OE5# IN
Active low input for enabling DIF pair 5.
1 =disable outputs, 0 = enable outputs
35 DIF_6 OUT 0.7V differential true clock output
36 DIF_6# OUT 0.7V differential Complementary clock output
