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9ZX21901BKLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
IDT
®
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI 1586P - 11/19/15
9ZX21901B
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
4
Pin Description (continued)
PIN # PIN NAME PIN TYPE DESCRIPTION
37 OE6# IN
Active low input for enabling DIF pair 6.
1 =disable outputs, 0 = enable outputs
38 DIF_7 OUT 0.7V differential true clock output
39 DIF_7# OUT 0.7V differential Complementary clock output
40 OE7# IN
Active low input for enabling DIF pair 7.
1 =disable outputs, 0 = enable outputs
41 DIF_8 OUT 0.7V differential true clock output
42 DIF_8# OUT 0.7V differential Complementary clock output
43 OE8# IN
Active low input for enabling DIF pair 8.
1 =disable outputs, 0 = enable outputs
44 GND PWR Ground pin.
45 VDD PWR Power supply, nominal 3.3V
46 DIF_9 OUT 0.7V differential true clock output
47 DIF_9# OUT 0.7V differential Complementary clock output
48 OE9# IN
Active low input for enabling DIF pair 9.
1 =disable outputs, 0 = enable outputs
49 DIF_10 OUT 0.7V differential true clock output
50 DIF_10# OUT 0.7V differential Complementary clock output
51 OE10# IN
Active low input for enabling DIF pair 10.
1 =disable outputs, 0 = enable outputs
52 DIF_11 OUT 0.7V differential true clock output
53 DIF_11# OUT 0.7V differential Complementary clock output
54 OE11# IN
Active low input for enabling DIF pair 11.
1 =disable outputs, 0 = enable outputs
55 DIF_12 OUT 0.7V differential true clock output
56 DIF_12# OUT 0.7V differential Complementary clock output
57 OE12# IN
Active low input for enabling DIF pair 12.
1 =disable outputs, 0 = enable outputs
58 VDD PWR Power supply, nominal 3.3V
59 DIF_13 OUT 0.7V differential true clock output
60 DIF_13# OUT 0.7V differential Complementary clock output
61 DIF_14 OUT 0.7V differential true clock output
62 DIF_14# OUT 0.7V differential Complementary clock output
63 GND PWR Ground pin.
64 DIF_15 OUT 0.7V differential true clock output
65 DIF_15# OUT 0.7V differential Complementary clock output
66 DIF_16 OUT 0.7V differential true clock output
67 DIF_16# OUT 0.7V differential Complementary clock output
68 VDD PWR Power supply, nominal 3.3V
69 DIF_17 OUT 0.7V differential true clock output
70 DIF_17# OUT 0.7V differential Complementary clock output
71 DIF_18 OUT 0.7V differential true clock output
72 DIF_18# OUT 0.7V differential Complementary clock output
IDT
®
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI 1586P - 11/19/15
9ZX21901B
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
5
Electrical Characteristics - Absolute Maximum Ratings
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
UNITS NOTES
3.3V Core Supply Voltage VDDA 4.6 V 1,2
3.3V Logic Supply Voltage VDD 4.6 V 1,2
Input Low Voltage V
IL
GND-0.5 V 1
Input High Voltage V
IH
Except for SMBus interface V
D
D
+0.5V V 1
Input High Voltage V
IHSMB
SMBus clock and data pins 5.5V V 1
Storage Temperature Ts -65 150
°
C
1
Junction Temperature Tj 125 °C 1
Case Temperature Tc 110 °C 1
Input ESD protection
ESD prot Human Body Model 2000 V 1
1
Guaranteed by desi
g
n and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor
g
uaranteed.
Electrical Characteristics - Input/Supply/Common Parameters
TA = T
COM;
Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Ambient Operating
Temperature
T
COM
Commmercial range 0 70 °C 1
Input High Voltage V
IH
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
2V
DD
+ 0.3 V 1
Input Low Voltage V
IL
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
GND
- 0.3 0.8 V 1
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 5 uA 1
I
INP
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
-200 200 uA 1
F
ib
yp
V
DD
= 3.3 V, Bypass mode 33 400 MHz 2
F
i
p
ll
V
DD
= 3.3 V, 100MHz PLL mode 90 100.00 105 MHz 2
F
i
p
ll
V
DD
= 3.3 V, 133.33MHz PLL mode 120 133.33 140 MHz 2
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
INDI F_IN
DIF_IN differential clock inputs 1.5 2.7 pF 1,4
C
OUT
Output pin capacitance 6 pF 1
Clk Stabilization T
STAB
From V
DD
Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
1.8 ms 1,2
Input SS Modulation
Frequency
f
MODIN
Allowable Frequency
(Triangular Modulation)
30 33 kHz 1
OE# Latency t
LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
412clocks1,3
Tdrive_PD# t
DRVPD
DIF output enable after
PD# de-assertion
300 us 1,3
Tfall t
Fall time of control inputs 5 ns 1,2
Trise t
R
Rise time of control inputs 5 ns 1,2
SMBus Input Low Voltage V
ILSMB
0.8 V 1
SMBus Input High Voltage V
IHSMB
2.1 V
DDSMB
V1
SMBus Output Low Voltage V
OLSMB
@ I
PULLUP
0.4 V 1
SMBus Sink Current I
PULLUP
@ V
OL
4mA1
Nominal Bus Voltage V
DDSMB
3V to 5V +/- 10% 2.7 5.5 V 1
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency
f
MAXSMB
Maximum SMBus operating frequency 100 kHz 1,5
1
Guaranteed by design and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swing.
5
The differential input clock must be running for the SMBus to be active
Input Current
3
Time from deassertion until out
p
uts are >200 mV
4
DIF_IN input
Capacitance
Input Frequency
IDT
®
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI 1586P - 11/19/15
9ZX21901B
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
6
Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs
TA = T
COM;
Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Slew rate dV/dt Scope averaging on 1 2.5 4
V/ns
1, 2, 3
Slew rate matching
∆dV/dt
Slew rate matching, Scope averaging on 20
%
1, 2, 4
Rise/Fall Time Matching
Trf Rise/fall matching, Scope averaging off 125
ps
1, 7, 8
Voltage High VHigh 660 750 850 1
Voltage Low VLow -150 150 1
Max Volta
g
eVmax 1150 1
Min Voltage Vmin -300 1
Vswing Vswing Scope averaging off 300 mV 1, 2
Crossing Voltage (abs) Vcross_abs Scope averaging off 250 550 mV 1, 5
Crossing Voltage (var)
∆
-Vcross Scope averaging off 140 mV 1, 6
2
Measured from differential waveform
7
Measured from single-ended waveform
8
Measured with scope averaging off, using statistics function. Variation is difference between min and max.
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross
absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.
mV
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
Measurement on single ended signal using
absolute value. (Scope averaging off)
mV
1
Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xR
R
). For R
R
= 475
Ω
(1%), I
REF
= 2.32mA.
I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
Ω
(100
Ω
differential impedance).
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
Electrical Characteristics - DIF_IN Clock Input Parameters
T
AMB
=T
COM
unless otherwise indicated, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input Crossover Voltage -
DIF_IN
V
CROSS
Cross Over Voltage 150 900 mV 1
Input Swing - DIF_IN V
SWING
Differential value 300 mV 1
Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 8 V/ns 1,2
Input Leakage Current I
IN
V
IN
= V
DD ,
V
IN
=
GND -5 5 uA
Input Duty Cycle d
tin
Measurement from differential wavefrom 45 55 % 1
Input Jitter - Cycle to Cycle J
DIFIn
Differential Measurement 0 125 ps 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured through +/-75mV window centered around differential zero
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

9ZX21901BKLF

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Buy 9ZX21901BKLF
Manufacturer:
IDT
Description:
Clock Buffer HIGH PERF. ZDB DB190 0Z w/External Fdbk
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