IDT
®
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI 1586P - 11/19/15
9ZX21901B
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
7
Electrical Characteristics - Current Consumption
TA = T
COM;
Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Operating Supply Current I
DD3.3OP
All outputs active @100MHz, C
L
= Full load;
407 500
mA 1
Powerdown Current
I
DD3.3PDZ
All differential pairs tri-stated 12 36 mA 1
1
Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - Skew and Differential Jitter Parameters
TA = T
COM;
Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
CLK_IN, DIF[x:0] t
SPO_PLL
Input-to-Output Skew in PLL mode
nominal value @ 25°C, 3.3V
-300 -200 -100 ps 1,2,4,5,8
CLK_IN, DIF[x:0] t
PD_BYP
Input-to-Output Skew in Bypass mode
nominal value @ 25°C, 3.3V
2.5 3.5 4.5 ns 1,2,3,5,8
CLK_IN, DIF[x:0] t
DSPO_PLL
Input-to-Output Skew Varation in PLL mode
across voltage and temperature
-50 0 50 ps 1,2,3,5,8
CLK_IN, DIF[x:0] t
DSPO_BYP
Input-to-Output Skew Varation in Bypass mode
across voltage and temperature
-250 250 ps 1,2,3,5,8
CLK_IN, DIF[x:0] t
DTE
Random Differential Tracking error beween two
9ZX devices in Hi BW Mode
35
ps
(rms)
1,2,3,5,8
CLK_IN, DIF[x:0] t
DSSTE
Random Differential Spread Spectrum Tracking
error beween two 9ZX devices in Hi BW Mode
15 75 ps 1,2,3,5,8
DIF{x:0] t
SKEW_ALL
Output-to-Output Skew across all outputs
(Common to Bypass and PLL mode)
45 65 ps 1,2,3,8
PLL Jitter Peaking j
eak-hibw
LOBW#_BYPASS_HIBW = 1 0 1 2.5 dB 7,8
PLL Jitter Peaking j
eak-lobw
LOBW#_BYPASS_HIBW = 0 0 1 2 dB 7,8
PLL Bandwidth pll
HIBW
LOBW#_BYPASS_HIBW = 1 2 3 4 MHz 8,9
PLL Bandwidth pll
LOBW
LOBW#_BYPASS_HIBW = 0 0.7 1 1.4 MHz 8,9
Duty Cycle t
DC
Measured differentially, PLL Mode 45 50 55 % 1
Duty Cycle Distortion t
DCD
Measured differentially, Bypass Mode
@100MHz
-2 0 2 % 1,10
PLL mode 24 50 ps 1,11
Additive Jitter in Bypass Mode 20 50 ps 1,11
Notes for preceding table:
6.
t is the period of the input clock
7
Measured as maximum pass band
ain. At frequencies within the loop BW, hi
hest point of ma
nification is called PLL jitter peakin
.
8.
Guaranteed by desi
n and characterization, not 100% tested in production.
9
Measured at 3 db down or half power point.
10
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
11
Measured from differential waveform
3
All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
4
This parameter is deterministic for a given device
1
Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input. Feedback
path is 695 mils long.
5
Measured with scope averaging on to find mean value. DIF_IN slew rate must be matched to DIF output slew rate.
2
Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.
Jitter, Cycle to cycle t
jcyc-cyc
