LPC2148FBD64,151 Datasheet LPC2148FBD64,151, LPC2142FBD64,151, LPC2141FBD64,151 | P16-P18

Product data sheet Rev. 5 — 12 August 2011 16 of 45

NXP Semiconductors

LPC2141/42/44/46/48

Single-chip 16-bit/32-bit microcontrollers

6.7 Fast general purpose parallel I/O (GPIO)

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back, as well as the current state of the port pins.

LPC2141/42/44/46/48 introduce accelerated GPIO functions over prior LPC2000 devices:

• GPIO registers are relocated to the ARM local bus for the fastest possible I/O timing.

• Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

• All GPIO registers are byte addressable.

• Entire port value can be written in one instruction.

6.7.1 Features

• Bit-level set and clear registers allow a single instruction set or clear of any number of

bits in one port.

• Direction control of individual bits.

• Separate control of output set and clear.

• All I/O default to inputs after reset.

6.8 10-bit ADC

The LPC2141/42 contain one and the LPC2144/46/48 contain two analog to digital

converters. These converters are single 10-bit successive approximation analog to digital

converters. While ADC0 has six channels, ADC1 has eight channels. Therefore, total

number of available ADC inputs for LPC2141/42 is 6 and for LPC2144/46/48 is 14.

6.8.1 Features

• 10 bit successive approximation analog to digital converter.

• Measurement range of 0 V to VREF (2.5 V  VREF  V

DDA

• Each converter capable of performing more than 400000 10-bit samples per second.

• Every analog input has a dedicated result register to reduce interrupt overhead.

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition on input pin or timer match signal.

• Global Start command for both converters (LPC2142/44/46/48 only).

6.9 10-bit DAC

The DAC enables the LPC2141/42/44/46/48 to generate a variable analog output. The

maximum DAC output voltage is the VREF voltage.

6.9.1 Features

• 10-bit DAC.

• Buffered output.

• Power-down mode available.

Product data sheet Rev. 5 — 12 August 2011 17 of 45

NXP Semiconductors

LPC2141/42/44/46/48

Single-chip 16-bit/32-bit microcontrollers

• Selectable speed versus power.

6.10 USB 2.0 device controller

The USB is a 4-wire serial bus that supports communication between a host and a

number (127 max) of peripherals. The host controller allocates the USB bandwidth to

attached devices through a token based protocol. The bus supports hot plugging,

unplugging, and dynamic configuration of the devices. All transactions are initiated by the

host controller.

The LPC2141/42/44/46/48 is equipped with a USB device controller that enables

12 Mbit/s data exchange with a USB host controller. It consists of a register interface,

serial interface engine, endpoint buffer memory and DMA controller. The serial interface

engine decodes the USB data stream and writes data to the appropriate end point buffer

memory. The status of a completed USB transfer or error condition is indicated via status

registers. An interrupt is also generated if enabled.

A DMA controller (available in LPC2146/48 only) can transfer data between an endpoint

buffer and the USB RAM.

6.10.1 Features

• Fully compliant with USB 2.0 Full-speed specification.

• Supports 32 physical (16 logical) endpoints.

• Supports control, bulk, interrupt and isochronous endpoints.

• Scalable realization of endpoints at run time.

• Endpoint maximum packet size selection (up to USB maximum specification) by

software at run time.

• RAM message buffer size based on endpoint realization and maximum packet size.

• Supports SoftConnect and GoodLink LED indicator. These two functions are sharing

one pin.

• Supports bus-powered capability with low suspend current.

• Supports DMA transfer on all non-control endpoints (LPC2146/48 only).

• One duplex DMA channel serves all endpoints (LPC2146/48 only).

• Allows dynamic switching between CPU controlled and DMA modes (only in

LPC2146/48).

• Double buffer implementation for bulk and isochronous endpoints.

6.11 UARTs

The LPC2141/42/44/46/48 each contain two UARTs. In addition to standard transmit and

receive data lines, the LPC2144/46/48 UART1 also provides a full modem control

handshake interface.

Compared to previous LPC2000 microcontrollers, UARTs in LPC2141/42/44/46/48

introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers

to achieve standard baud rates such as 115200 with any crystal frequency above 2 MHz.

In addition, auto-CTS/RTS flow-control functions are fully implemented in hardware

(UART1 in LPC2144/46/48 only).

Product data sheet Rev. 5 — 12 August 2011 18 of 45

NXP Semiconductors

LPC2141/42/44/46/48

Single-chip 16-bit/32-bit microcontrollers

6.11.1 Features

• 16 B Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• Transmission FIFO control enables implementation of software (XON/XOFF) flow

control on both UARTs.

• LPC2144/46/48 UART1 equipped with standard modem interface signals. This

module also provides full support for hardware flow control (auto-CTS/RTS).

6.12 I

C-bus serial I/O controller

The LPC2141/42/44/46/48 each contain two I

C-bus controllers.

The I

C-bus is bidirectional, for inter-IC control using only two wires: a Serial Clock Line

(SCL), and a Serial DAta line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the

capability to both receive and send information (such as memory)). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I

C-bus is a multi-master bus, it can be

controlled by more than one bus master connected to it.

The I

C-bus implemented in LPC2141/42/44/46/48 supports bit rates up to 400 kbit/s

(Fast I

C-bus).

6.12.1 Features

• Compliant with standard I

C-bus interface.

• Easy to configure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I

C-bus can be used for test and diagnostic purposes.

6.13 SPI serial I/O controller

The LPC2141/42/44/46/48 each contain one SPI controller. The SPI is a full duplex serial

interface, designed to handle multiple masters and slaves connected to a given bus. Only

a single master and a single slave can communicate on the interface during a given data

transfer. During a data transfer the master always sends a byte of data to the slave, and

the slave always sends a byte of data to the master.

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LPC2148FBD64,151

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NXP Semiconductors

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ARM Microcontrollers - MCU ARM7 512KF/40KR/USB

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LPC2148FBD64,151

LPC2148FBD64,151

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