LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 12 August 2011 30 of 45
NXP Semiconductors
LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers
9. Dynamic characteristics
[1] Characterized but not implemented as production test. Guaranteed by design.
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
[3] Bus capacitance C
b
in pF, from 10 pF to 400 pF.
Table 6. Dynamic characteristics of USB pins (full-speed)
C
L
= 50 pF; R
pu
= 1.5 k
on D+ to V
DD
, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
t
r
rise time 10 % to 90 % 4 - 20 ns
t
f
fall time 10 % to 90 % 4 - 20 ns
t
FRFM
differential rise and fall time
matching
(t
r
/t
f
)90-110%
V
CRS
output signal crossover voltage 1.3 - 2.0 V
t
FEOPT
source SE0 interval of EOP see Figure 7 160 - 175 ns
t
FDEOP
source jitter for differential transition
to SE0 transition
see Figure 7 2-+5ns
t
JR1
receiver jitter to next transition 18.5 - +18.5 ns
t
JR2
receiver jitter for paired transitions 10 % to 90 % 9-+9ns
t
EOPR1
EOP width at receiver must reject as
EOP; see
Figure 7
[1]
40 --ns
t
EOPR2
EOP width at receiver must accept as
EOP; see
Figure 7
[1]
82 --ns
Table 7. Dynamic characteristics
T
amb
=
40
C to +85
C for commercial applications, V
DD
over specified ranges
[1]
Symbol Parameter Conditions Min Typ
[2]
Max Unit
External clock
f
osc
oscillator frequency 10 - 25 MHz
T
cy(clk)
clock cycle time 40 - 100 ns
t
CHCX
clock HIGH time T
cy(clk)
0.4 - - ns
t
CLCX
clock LOW time T
cy(clk)
0.4 - - ns
t
CLCH
clock rise time - - 5 ns
t
CHCL
clock fall time - - 5 ns
Port pins (except P0.2, P0.3, P0.11, and P0.14)
t
r(o)
output rise time - 10 - ns
t
f(o)
output fall time - 10 - ns
I
2
C-bus pins (P0.2, P0.3, P0.11, and P0.14)
t
f(o)
output fall time V
IH
to V
IL
20 + 0.1 C
b
[3]
--ns
