DS1225AB/AD
7 of 9
NOTES:
1.
is high for a read cycle.
2.
= V
IH
or V
IL
. If
= V
IH
during write cycle, the output buffers remain in a high-impedance
state.
3. t
WP
is specified as the logical AND of
and
. t
WP
is measured from the latter of
or
going low to the earlier of
or
going high.
4. t
DS
are measured from the earlier of
or
going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the
low transition occurs simultaneously with or later than the
low transition, the output
buffers remain in a high-impedance state during this period.
7. If the
high transition occurs prior to or simultaneously with the
high transition, the output
buffers remain in a high-impedance state during this period.
8. If
is low or the
low transition occurs prior to or simultaneously with the
low transition,
the output buffers remain in a high-impedance state during this period.
9. Each DS1225AB and each DS1225AD has a built-in switch that disconnects the lithium source until
V
CC
is first applied by the user. The expected t
DR
is defined as accumulative time in the absence of
V
CC
starting from the time power is first applied by the user. This parameter is guaranteed by design
and is not 100% tested.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to
+85°C.
11. In a power down condition the voltage on any pin may not exceed the voltage on V
CC
.
12. t
WR1
, t
DH1
are measured from
going high.
13. t
WR2
, t
DH2
are measured from
going high.
14. DS1225 modules are recognized by Underwriters Laboratories (UL) under file E99151.
DC TEST CONDITIONS
Outputs Open
Cycle = 200ns for Operating Current
All Voltages Are Referenced to Ground
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate
Input Pulse Levels: 0 - 3.0V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
