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DS1852B-000

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DS1852
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Once the device address is clocked in and acknowledged by the DS1852 with the R/W bit set to high,
the current address data word is clocked out. The master does not respond with a zero, but does generate
a stop condition afterwards.
RANDOM READ
A random read requires a dummy byte write sequence to load in the data word address. Once the device
and data address bytes are clocked in by the master, and acknowledged by the DS1852, the master must
generate another start condition. The master now initiates a current address read by sending the device
address with the R/W bit set high. The DS1852 will acknowledge the device address and serially clocks
out the data byte.
SEQUENTIAL ADDRESS READ
Sequential reads are initiated by either a current address read or a random address read. After the master
receives the first data byte, the master responds with an acknowledge. As long as the DS1852 receives
this acknowledge after a byte is read, the master may clock out additional data words from the DS1852.
After reaching address FFh, it resets to address 00h.
The sequential read operation is terminated when the master initiates a stop condition. The master does
not respond with a zero.
For a more detailed description of 2-wire theory of operation, see 2-WIRE SERIAL PORT OPERATION.
DS1852
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2-WIRE SERIAL PORT OPERATION
The 2-wire serial port interface supports a bidirectional data transmission protocol with device
addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as
a receiver. The device that controls the message is called a “master.” The devices that are controlled by
the master are “slaves”. A master device that generates the serial clock (SCL), controls the bus access,
and generates the START and STOP conditions must control the bus. The DS1852 operates as a slave
on the 2-wire bus. Connections to the bus are made through the open-drain I/O lines SDA and SCL. The
following I/O terminals control the 2-wire serial port: SDA, SCL, and ASEL. Timing diagrams for the
2-wire serial port can be found in Figures 2 and 3. Timing information for the 2-wire serial port is
provided in the AC ELECTRICAL CHARACTERISTICS table for 2-wire serial communications.
The following bus protocol has been defined:
§ Data transfer may be initiated only when the bus is not busy.
§ During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
the data line while the clock line is HIGH will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line from HIGH to LOW while the clock is HIGH
defines a START condition.
Stop data transfer: A change in the state of the data line from LOW to HIGH while the clock line is
HIGH defines the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the HIGH period of the clock signal. The data on the line can be changed
during the LOW period of the clock signal. There is one clock pulse per bit of data. Figures 2 and 3
detail how data transfer is accomplished on the 2-wire bus. Depending upon the state of the R/W bit, two
types of data transfer are possible.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a
ninth bit.
Within the bus specifications a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate)
are defined. The DS1852 works in both modes.
Acknowledge: Each receiving device, when addressed, is obliged to generate an ‘acknowledge’ after
the byte has been received. The master device must generate an extra clock pulse, which is associated
with this acknowledge bit.
DS1852
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A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is a stable LOW during the HIGH period of the acknowledge-related clock pulse.
Of course, setup and hold times must be taken into account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.
1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is
the command/control byte. Next follows a number of data bytes. The slave returns an acknowledge
bit after each received byte.
2) Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the
command/control byte) to the slave. The slave then returns an acknowledge bit. Next follows a
number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit
after all received bytes other than the last byte. At the end of the last received byte, a ‘not
acknowledge’ can be returned.
The master device generates all serial clock pulses and the START and STOP conditions. A transfer is
ended with a STOP condition or with a repeated START condition. Since a repeated START condition
is also the beginning of the next serial transfer, the bus will not be released.
The DS1852 may operate in the following two modes:
1) Slave receiver mode: Serial data and clock are received through SDA and SCL, respectively. After
each byte is received, an acknowledge bit is transmitted. START and STOP conditions are
recognized as the beginning and end of a serial transfer. Address recognition is performed by
hardware after reception of the slave (device) address and direction bit.
2) Slave transmitter mode: The first byte is received and handled as in the slave receiver mode.
However, in this mode the direction bit will indicate that the transfer direction is reversed. Serial
data is transmitted on SDA by the DS1852 while the serial clock is input on SCL. START and STOP
conditions are recognized as the beginning and end of a serial transfer.
Slave Address: Command/control byte is the first byte received following the START condition from
the master device. The command/control byte consists of a 4-bit control code. For the DS1852, this is set
as 1010 000 (when ASEL is ‘0’) binary for R/W operations. The last bit of the command/control byte
(R/W) defines the operation to be performed. When set to a 1 a read operation is selected, and when set
to a 0 a write operation is selected.
Following the START condition, the DS1852 monitors the SDA bus checking the device type identifier
being transmitted. Upon receiving the chip address control code, and the R/W bit, the slave device
outputs an acknowledge signal on the SDA line.
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DS1852B-000

Mfr. #:
Buy DS1852B-000
Manufacturer:
Maxim Integrated
Description:
Data Acquisition ADCs/DACs - Specialized Optical Transceiver Diagnostic Monitor
Lifecycle:
New from this manufacturer.
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