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DS1852B-000

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
DS1852
16 of 26
Table 00h (Lower)
Memory Location
(Table 00h, Lower)
Name of Location Function
00h – 5Fh IEEE Data This memory block is used to store required GBIC data.
60h Temperature MSB This byte contains the MSB of the 15-bit 2’s complement
temperature output from the temperature sensor.
61h Temperature LSB This byte contains the LSB of the 15-bit 2’s complement
temperature output from the temperature sensor.
62h – 63h V
cc
Value These bytes contain the MSB (62h) and the LSB (63h) of the
measured V
CC
.
64h – 65h B
in
Value These bytes contain the MSB (64h) and the LSB (65h) of the
measured B
in.
66h – 67h P
in
Value These bytes contain the MSB (66h) and the LSB (67h) of the
measured P
in.
68h – 69h R
in
Value These bytes contain the MSB (68h) and the LSB (69h) of the
measured R
in.
6Eh IO States Bit 0 will be 0 when the analog monitoring is active.
6Fh A/D Updated Allows the user to verify if an update from the A/D has occurred to
the five values: temperature, V
CC
, B
in
, P
in
and R
in
. The user writes
the byte to 00h. Once a conversion is complete for a given value, its
bit will change to ‘1’.
70h – 73h Alarm Flags These bits reflect the state of the alarms as a conversion updates.
High alarm bits are ‘1’ if converted value is greater than
corresponding high limit. Low alarm bits are ‘1’ if converted value
is less than corresponding low limit. Otherwise, bits are ‘0’.
74h – 77h Warning Flags These bits reflect the state of the warnings as a conversion updates.
High warning bits are ‘1’ if converted value is greater than
corresponding high limit. Low warning bits are ‘1’ if converted
value is less than corresponding low limit. Otherwise, bits are ‘0’.
7Bh – 7Eh Password Entry Bytes
PWE Byte 3 (7Bh) MSByte
PWE Byte 2 (7Ch)
PWE Byte 1 (7Dh)
PWE Byte 0 (7Eh) LSByte
The four bytes are used for password entry. The entered password
will determine the user’s R/W privileges. During power-up these
bits are set to all 1s.
7Fh Table Select Byte This byte determines which of the upper memory pages are
selected.
00h — No physical memory
01h — Manufacturer EEPROM
02h — Manufacturer EEPROM
03h — Device settings
DS1852
17 of 26
Table 00h (Upper)
Address
Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7
bits<7-0> bits<7-0> bits<7-0> bits<7-0> bits<7-0> bits<7-0> bits<7-0> bits<7-0>
80h
…
…
F8h
Reserved by IEEE
(no physical memory)
Table 01h (Upper)
Address
Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7
bits<7-0> bits<7-0> bits<7-0> bits<7-0> bits<7-0> bits<7-0> bits<7-0> bits<7-0>
80h
…
…
F0h
Manufacturer EEPROM
(Read Access – Level 1, Write Access – Level 1)
F8h reserved
Address FFh is RAM
Table 02h (Upper)
Address
Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7
bits<7-0> bits<7-0> bits<7-0> bits<7-0> bits<7-0> bits<7-0> bits<7-0> bits<7-0>
80h
…
…
F8h
Manufacturer EEPROM
(Read Access – Level 2, Write Access – Level 2)
DS1852
18 of 26
Table 03h (Upper)
Address Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7
bits<7-0> bits<7-0> bits<7-0> bits<7-0> bits<7-0> bits<7-0> bits<7-0> bits<7-0>
HI ALARM LO ALARM HI WARN LO WARN
80h T alarm MSB T alarm LSB T alarm MSB T alarm LSB T warn MSB T warn LSB T warn MSB T warn LSB
88h V alarm MSB V alarm LSB V alarm MSB V alarm LSB V warn MSB V warn LSB V warn MSB V warn LSB
90h B alarm MSB B alarm LSB B alarm MSB B alarm LSB B warn MSB B warn LSB B warn MSB B warn LSB
98h P alarm MSB P alarm LSB P alarm MSB P alarm LSB P warn MSB P warn LSB P warn MSB P warn LSB
A0h R alarm MSB R alarm LSB R alarm MSB R alarm LSB R warn MSB R warn LSB R warn MSB R warn LSB
A8h reserved reserved reserved reserved reserved reserved reserved reserved
B0h reserved reserved reserved reserved reserved reserved reserved reserved
B8h reserved reserved reserved reserved reserved reserved reserved reserved
C0h reserved reserved reserved reserved reserved reserved reserved reserved
C8h
V-ad scale MSB V-ad scale LSB B-ad scale MSB B-ad scale LSB P-ad scale MSB P-ad scale LSB R-ad scale MSB R-ad scale LSB
D0h chip address reserved reserved PW1 Byte 3 PW1 Byte 2 PW1 Byte 1 PW1 Byte 0 reserved
D8h B Fast trip0 B Fast trip1 B Fast trip2 B Fast trip3 B Fast trip4 B Fast trip5 B Fast trip6 B Fast trip7
E0h P Fast trip0 P Fast trip1 P Fast trip2 P Fast trip3 R Fast trip0 R Fast trip1 R Fast trip2 R Fast trip3
E8h config/o-ride reserved reserved reserved reserved reserved reserved reserved
F0h reserved reserved reserved reserved reserved reserved reserved reserved
F8h reserved reserved reserved reserved reserved reserved reserved reserved
Address E8h is RAM.
Read Access – Level 2, Write Access – Level 2
Fast-Trip Temperature Relationships
Fast Trip
Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7
bits<7-0> bits<7-0> bits<7-0> bits<7-0> bits<7-0> bits<7-0> bits<7-0> bits<7-0>
* B-in
< –8
[-8 to 8) [8 to 24)
[24 to 40)
[40 to 56)
[56 to 72)
[72 to 88)
³ 88
* P-in
< 8
[8 to 40)
[40 to 72)
³ 72
* R-in
< 8
[8 to 40)
[40 to 72)
³ 72
* There is one degree of hysteresis at transitions only (e.g., for B-in, if temp increases to +8.0°C then byte 2 is active. It will
remain active until temp reaches +24.0°C or falls below +7.0°C.).
Table 03h (Expanded)
Byte Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Chip address
b
7
b
6
b
5
b
4
b
3
b
2
b
1
X
X-ad scale
MSB*
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
X-ad scale
LSB*
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
config/O-ride
reserved reserved manual AD
alarm
EE Bar SW-POR A/D Enable Manual fast
alarm
reserved
* V-, B-, P- or R- as appropriate
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

DS1852B-000

Mfr. #:
Buy DS1852B-000
Manufacturer:
Maxim Integrated
Description:
Data Acquisition ADCs/DACs - Specialized Optical Transceiver Diagnostic Monitor
Lifecycle:
New from this manufacturer.
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