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DS1852B-000

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
DS1852
22 of 26
AC ELECTRICAL CHARACTERISTICS (-40
°
C to +100
°
C, V
CC
= 2.7V to 5.5V)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
SCL Clock
Frequency
f
SCL
Fast Mode
Standard Mode
0
0
400
100
kHz 7
Bus Free Time
Between STOP and
START Condition
t
BUF
Fast Mode
Standard Mode
1.3
4.7
µs 7
Hold Time
(Repeated)
START Condition
t
HD:STA
Fast Mode
Standard Mode
0.6
4.0
µs 7, 8
Low Period of SCL
Clock
t
LOW
Fast Mode
Standard Mode
1.3
4.7
µs 7
High Period of SCL
Clock
t
HIGH
Fast Mode
Standard Mode
0.6
4.0
µs 7
Data Hold Time t
HD:DAT
Fast Mode
Standard Mode
0
0
0.9 µs 7, 9, 10
Data Setup Time t
SU:DAT
Fast Mode
Standard Mode
100
250
ns 7
Start Setup Time t
SU:STA
Fast Mode
Standard Mode
0.6
4.7
µs 7
Rise Time of Both
SDA and SCL
Signals
t
R
Fast Mode
Standard Mode
20+0.1C
B
300
1000
ns 11
Fall Time of Both
SDA and SCL
Signals
t
F
Fast Mode
Standard Mode
20+0.1C
B
300
300
ns 11
Setup Time for STOP
Condition
t
SU:STO
Fast Mode
Standard Mode
0.6
4.0
µs
Capacitive Load for
Each Bus Line
C
B
400 pF 11
Startup Time t
ST
2 ms 5
V
CC
Power-Up Rate 1 V/s
EEPROM Write
Time
t
W
10 20 ms 6
NONVOLATILE MEMORY CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Writes +85°C 50,000
DS1852
23 of 26
NOTES
1) All voltages are referenced to ground.
2) This is the time for one comparison. The complete cycle is this value multiplied by 3.
3) Absolute voltage error for B
in
, P
in
, and R
in
are valid from 0% to 98%.
4) ASEL = GND, SDA = SCL = D
in
= F
in
= L
in
= RS
in
= V
CC
.
5) The time to begin monitoring operations after V
CC
has risen above the analog minimum voltage.
6) After STOP command has been received. No acknowledges will be issued during this interval.
7) A fast mode device can be used in a standard mode system, but the requirement t
SU:DAT
> 250ns must
then be met. This will automatically be the case if the device does not stretch the low period of the
SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next
data bit to the SDA line t
RMAX
+ t
SU:DAT
= 1000 + 250 = 1250ns before the SCL line is released.
8) After this period, the first clock pulse is generated.
9) The maximum t
HD:DAT
has only to be met if the device does not stretch the low period (t
LOW
) of the
SCL signal.
10) A device must internally provide a hold time of at least 300ns for the SDA signal (see the V
IH MIN
of
the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
11) C
B
— total capacitance of one bus line in picofarads, timing referenced to 0.9V
CC
and 0.1V
CC
.
12) Input levels equal either V
CC
or GND.
DS1852
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SCALING THE ADC
procedure writeTrimValue(trim :integer); (* write trim to part *)
procedure forceReference(Vin: real); (* applies reference voltage to input pin*)
procedure waitForNewConversion(); (* writes update byte to zero and waits for update
of new conversion with present trim *)
function readValue():integer; (* reads converted digital answer *)
procedure ProgramTrim(trim :integer);(*enables EE for table3 & programs trim*)
Procedure calVad(maxInput :real)
var
Bit :integer; (* counter - represents bininary bit 15-0*)
trim :integer; (* present trim values *)
lsb :real; (* the lsb value of the voltage reading *)
Vin :real; (* the reference input voltage *)
Dec_in :integer; (* decimal representation of voltage input *)
Dec_out :integer; (* voltage reading in decimal *)
delta :integer; (* present error of voltage reading *)
bestDelta :integer; (* the error closest to zero *)
bestTrim :integer; (* the trim that gave the best delta *)
Begin
bestDelta := 1000000;
bestTrim := 0;
trim := 4095; (* 0FFFh *)
lsb := maxInput / 65535;
Dec_in := 63888; (* input is ~97.5% of full scale *)
Vin := lsb * Dec_in;
forceReference(Vin);
(*Use SAR approach to trim course adjust on VAD scale bits 15-12*)
for Bit := 15 downto 11 do (* must go 1 bit too far so that zero is
possible solution *)
begin
if (Bit > 11) then
begin
trim := trim + lshft(1,Bit);
end;
writeTrimValue(trim);
waitForNewConversion;
Dec_out := readVoltage;
delta := Dec_out - Dec_in;
if ( delta >= 0 ) then
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

DS1852B-000

Mfr. #:
Buy DS1852B-000
Manufacturer:
Maxim Integrated
Description:
Data Acquisition ADCs/DACs - Specialized Optical Transceiver Diagnostic Monitor
Lifecycle:
New from this manufacturer.
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