LOW SKEW, 1-TO-9
LVCMOS / LVTTL CLOCK MULTIPLIER
87950I DATA SHEET
2 REVISION C 11/6/15
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
Number Name Type Description
1V
DDA
Power Analog supply pin.
2 FBDIV_SEL Input Pulldown
Selects divide value for Bank feedback output as described in
Table 3E. LVCMOS / LVTTL interface levels.
3 DIV_SELA Input Pulldown
Selects divide value for Bank A output as described in Table 3D.
LVCMOS / LVTTL interface levels.
4 DIV_SELB Input Pulldown
Selects divide value for Bank B output as described in Table 3D.
LVCMOS / LVTTL interface levels.
5 DIV_SELC Input Pulldown
Selects divide value for Bank C outputs as described in Table 3D.
LVCMOS / LVTTL interface levels.
6 DIV_SELD Input Pulldown
Selects divide value for Bank D outputs as described in Table 3D.
LVCMOS / LVTTL interface levels.
7, 13, 17,
21, 25, 29
GND Power Power supply ground.
8,
9
XTAL_IN, XTAL_
OUT
Input
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
10 MR/nOE Input Pulldown
Active High Master Reset. Active Low Output Enable. When logic HIGH,
the internal dividers are reset and the outputs are tri-stated (HiZ). When
logic LOW, the internal dividers and the outputs are enabled. LVCMOS /
LVTTL interface levels.
11, 15, 19,
23, 27
V
DDO
Power Output supply pins.
12, 14,
16, 18, 20
QD4, QD3,
QD2, QD1, QD0
Output
Bank D clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
22, 24 QC1, QC0 Output
Bank C clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
26 QB Output
Bank B clock output. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
28 QA Output
Bank A clock output. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
30 CLK Input Pulldown LVCMOS / LVTTL phase detector reference clock input.
31 PLL_SEL Input Pulldown
Selects between the PLL and the reference clock as the input to the
dividers. When HIGH, selects PLL. When LOW, selects the reference
clock. LVCMOS / LVTTL interface levels.
32 CLK_SEL Input Pulldown
Clock select input. When HIGH, selects CLK. When LOW,
selects XTAL_IN, XTAL _OUT. LVCMOS / LVTTL interface levels.
NOTE:
Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
C
PD
Power Dissipation Capacitance (per output) V
DDA
, V
DDO
= 3.47V 25 pF
R
PULLDOWN
Input Pulldown Resistor 51
kΩ
R
OUT
Output Impedance 5 7 12
Ω
